August 7, 2012 -- This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SOC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.
Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.
Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, SystemVerilog, Universal Verification Methodology, UVM, verification IP, intellectual property, cores, Synopsys, EE Times Education & Training
336/38861 8/7/2012 672 160
Designer's Mall
0.015625
Subscribe to SOCcentral's SOC Explorer Newsletter and receive news, article, whitepaper, and product updates bi-weekly.
