November 30, 2004 -- Sierra Design Automation, Inc. has entered into an agreement with ATI Technologies, Inc. to license its Sierra Pinnacle physical synthesis tool for use on ATI's industry-leading designs. ATI selected Sierra Pinnacle after a year-long collaboration and extensive evaluations over multiple, challenging designs.
"Our complex, high-performance designs demand very high quality results and fast turn-around times from our physical design implementation flow," said Greg Buchner, VP of Engineering, ATI Technologies Inc. "The addition of Sierra Pinnacle to our arsenal enables our designers to meet their challenging design goals."
Sierra Pinnacle is an IC implementation solution developed specifically to meet the high capacity, short turn around time and quality of results (QoR) demands of large designs targeted at manufacturing processes of 90 nanometer and below. According to the company, its physical synthesis technology and product architecture speeds design closure by 5x to 10x, slashing turnaround time from days to hours, and eliminating a major recognized bottleneck in the physical design of multi-million gate nanometer chips. Pinnacle's open architecture and ultra-compact database can handle 10 Million gates flat - chips or blocks - on a 32-bit machine. Pinnacle scales to 50+ Million gate hierarchical designs on a 64-bit machine and seamlessly integrates into customer's existing design flows.