December 15, 2004 -- eASIC Corp. today announced that the company was granted an additional patent for its technology. The patent entitled "Customizable and programmable cell array" (6,819,136), issued on November 16, 2004 by the United States Patent and Trademark Office, is a continuation of a previous patent (6,756,811) granted to eASIC in the area of chip customization. This patent protects the company’s unique configurable logic technology, which utilizes electrical programmable cells connected with lithography-defined custom interconnections. The patent also protects the use of a coarse-grain array fabric, where each cell comprises of flip-flops with some fine grain functions such as inverters or multiplexers used as logic gates.

eASIC’s patent portfolio protects the company’s Configurable Logic and Structured ASIC products from competing technologies attempting to use similar techniques to address today’s deep submicron design issues. According to eASIC, it is the only company which has successfully integrated in one fabric FPGA-like logic programmability (SRAM-LUT) combined with segmented standard metal routing, customized by a single via-layer. This unique technology allows eASIC to offer fast-turn Structured ASIC products without NRE (Non Recurring Engineering) cost, by using efficiently existing maskless customization technique of Direct-Write eBeam.