April 5, 2004 -- Extending its range of leading serializer/deserializer (SerDes) offerings, Texas Instruments, Inc. announced that its 6.25 Gbps high-speed serial interface circuitry is now available in its 90nm CMOS process technology, and for integration into customer high-speed ASIC designs. By migrating 6.25 Gbps SerDes to TI's proven 90nm advanced process technology, customers can design next-generation ASIC products integrating 200 or more 6.25 Gbps channels, and the industry's lowest power of 185 milliwatts (mW) per channel.

"TI's continued investment in process technology and manufacturing allow communications equipment makers to meet their high density, low power requirements without replacing existing architectures," said Steve Sutton, vice president of TI's ASIC business unit. "By leveraging TI's SerDes design and 90nm process expertise, designers can achieve reliable and flexible system designs, with increased performance and reduced size, power and cost."

TI's 6.25 Gbps technology was initially developed in the company's 130nm process and is designed in ASIC products today and available in TI's standard product portfolio. The migration to manufacturing in 90nm CMOS allows customers to upgrade existing network infrastructure systems without legacy backplane replacements, preserving previous technology investments made by system manufacturers.

TI's 6.25 Gbps SerDes technology reduces application risk by utilizing a two-level binary signaling approach, ensuring backward compatibility, interoperability and scalability with existing and next generation capabilities and standards. Together with advanced transmit pre-emphasis, the receiver includes a high gain adaptive linear equalizer to compensate for ISI and cross-talk, which is essential for operating in legacy system environments.

TI's 90nm process was developed to deliver the integration and circuit optimization required to match device architectures with targeted application areas. Transistors are "tuned" for different functions on a single chip to meet a variety of performance, density and power consumption requirements by adjusting the transistors' gate length, threshold voltage, gate oxide thickness or bias conditions. As a result, the highest performing transistors are used for critical functions such as signal processing, whereas transistors with lower power consumption are used for functions with lower active performance requirements.

The 90nm process features up to eight layers of metal and integrates a low-k dielectric, Organo-Silicate Glass (OSG) that has a k-value of 2.8. TI has extended its history as an innovator in gate dielectric materials, as its 90nm process is TI's third generation to use a Plasma Nitrided Oxide (PNO) for the core transistors. PNO maintains the transistors' high levels of reliability, minimizes gate leakage and allows TI's 90nm technology to meet benchmarks.

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