April 5, 2004 -- The new high performance MIPS32 24K processor core family from MIPS Technologies, Inc. is using the on-chip interconnect technology developed by the Open Core Protocol International Partnership (OCP-IP) as its native interface, the companies announced today. The OCP standard facilitates "plug-and-play" SOC design, and helps customers exploit the new core family’s advanced architectural features, reduce development time and lower overall design costs.
The OCP standard reduces development time and lowers risk and costs by allowing designers who use the 24K core to reuse OCP-compliant cores across multiple MIPS-Based SOCs. OCP also eliminates the need to repeatedly modify the core and preserves the verification and test benches by defining all of the core’s natural interface capabilities in a standardized way. These interface definitions enable third party verification IP and tools to transparently adjust to the precise requirements of each IP. Furthermore, designers can take advantage of MIPS Technologies’ SOC-it system-level controller optimized for OCP, which provides a tightly coupled memory controller and includes a bridge to other on-chip system buses.
"Standard interfaces and buses are critical in meeting the challenges of increasingly complex SOC design and shrinking market windows, and MIPS Technologies is pleased to support OCP-IP’s effort to make plug-and-play SOC design a reality," said Tom Petersen, director of product marketing at MIPS Technologies. "Those who choose to take advantage of OCP can bring their 24K core-based designs to market quickly, easily and efficiently, with less risk and lower cost."
"We're delighted to have OCP featured as the native interface in the industry’s highest performance 32-bit cores," said Ian Mackintosh, president of OCP-IP. "By utilizing OCP, customers of the 24K cores can free up critical engineering resources and more quickly achieve their design goals."
The MIPS32 24K core family, which includes the 24Kc, 24Kc Pro, 24Kf and 24Kf Pro versions, offers performance from 400 to 550 MHz worst case in a 0.13 micron process, the highest frequency available in 32-bit synthesizable cores for embedded markets, while minimizing design time and reducing product costs. Tailored SOC design methodologies, an Open Core Protocol (OCP) interconnect structure, standard libraries and on-chip memories from industry-leading companies help speed time-to-market, an important advantage for a processor core suited to embedded consumer applications such as digital and interactive TVs, set-top boxes and DVD players.
Go to the MIPS Technologies, Inc. website to find additional information.