July 18, 2006 -- Golden Gate Technology, Inc. has improved the power reduction capabilities and run time of its flagship software product, PowerGold (formerly called Power Optimize Gold). PowerGold version 6.2 reduces power consumption 10% to 20% or more and runs 2X to 3X faster than the previous version, announced last year. It complements industry-standard cell physical design flows, such as those supported by Cadence Design Systems, Inc., Magma Design Automatio, Inc. and Synopsys, Inc..

Power Gold version 6.2 achieves faster runtimes through improvements in the core power optimization algorithms. In addition, new logic restructuring algorithms further reduce power consumption. PowerGold can reduce both dynamic and leakage power, with an average power reduction of more than 15% across typical designs. PowerGold's power reduction capability has been validated on more than 10 customer designs done with Cadence, Magma, and Synopsys physical design flows in 90-nm and 13- nm process technologies.

PowerGold reduces power at several stages in the physical design flow. It works with placement and clock tree synthesis to reduce power consumption in critical clock networks. Because wires account for 5X more power consumption than transistors at the 90-nm node, and are projected to account for 30X more power consumption than transistors at 35nm, Golden Gate's power reduction software gives wires priority with its patent-pending optimization technology called WiresFirst. WiresFirst minimizes total capacitance on critical clock and signal nets through route optimization and isolation techniques that reduce power without negatively impacting chip timing, signal integrity or electromigration.

Consistent with a wire-centric approach, PowerGold employs the WiresFirst Routing Prototype Engine at the placement stage to minimize clock wire capacitance. After initial routing, WiresFirst algorithms incrementally rebalance capacitances and restructure logic to reduce excess power consumption with minimal perturbation to a design's timing and physical layout characteristics. Various power reduction techniques implemented by PowerGold are cumulative.

PowerGold supports multiple threshold voltage cell libraries to reduce leakage current without negatively impacting timing. Because PowerGold reduces wire capacitance with the WiresFirst algorithm, low-leakage cells are used more frequently than in traditional design flows, resulting in greater leakage power reduction. PowerGold has the capacity to reduce power on large designs – up to 10M gates in an overnight run on a 32-bit OS or unlimited gate size on a 64-bit OS.

Pricing and Availability

PowerGold version 6.2 is available now for Solaris and Linux.