Page loading . . .

  
 Category: News: News Archive 2006: Friday, May 24, 2013
Texas Instruments Releases to Production PCI Express x1 Physical Layer Device  
 Printer friendly
 E-Mail Item URL

August 2, 2006 -- Texas Instruments, Inc. (TI) announced today full-production release of its new PCI Express x1 physical layer (PHY) device, the XIO1100. The XIO1100 is targeted at markets demanding low-cost PCIe end-point solutions such as data acquisition, industrial, networking and communication, medical and imaging, as well as consumer and video. XIO1100 is compliant with the PCI Express Base Specification Revision 1.1 and PHY Interface for the PCI Express Architecture (PIPE) 1.0.

XIO1100's flexible MAC interface supports both source synchronous and DDR clocking. "This offers distinct advantages to designers in terms of faster time to market and enabling lower cost solutions," said Jawaid Ahmad, Strategic Product Marketing Manager for TI's digital interface business unit. "SS clocking makes I/O layout robust and painless while DDR clocking offers our customers the opportunity to choose low-cost FPGAs which do not run faster than 125MHz."

Adding to its list of features, the XIO1100 has an integrated adaptive equalizer in its receive link, providing system design flexibility and reliably increasing interconnect length supported by the XIO1100.

Pricing and Availability

The XIO1100 is available today in a 100-pin MicroStar BGA in Pb or Pb- free RoHS-compliant package. 1K unit reference price is $7/unit. TI also offers third-party development kits based on XIO1100 and Cyclone II or Spartan 3 FPGAs.

Go to the Texas Instruments, Inc. (TI) website for details.

Read more about
Texas Instruments, Inc. (TI)
on SOCcentral.com


Keywords: Texas Instruments (TI), PCI Express, PCIe,
552/19785 8/2/2006 1243 342


Designer's Mall
0.390625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.552  0.46875