August 22, 2006 -- X-FAB Semiconductor Foundries AG is implementing Cadence Design Systems, Inc.'s Virtuoso NeoCircuit DFM solution to identify and eliminate yield-related problems early in the design phase and fabrication process. The product avoids the tedious and manually intensive task of sizing and optimizing a circuit topology in terms of process tolerances, voltage and temperature variations (P-V-T). Virtuoso NeoCircuit DFM overcomes the difficulty of estimating yield and optimization when IP is over-constrained in area and power consumption, or is optimized for a special corner.
Although X-FAB's analog and mixed-signal IP tolerates varying technology and operating conditions, robust, reliable designs must be verified throughout the entire range of process tolerances, voltage and temperature variations (P-V-T). Designs also are impacted by circuit optimizations – the central design phase in which performance conflicts are settled through trade-offs or compromises. Often, multiple corner combinations are required to fully capture the entire P-V-T corner performance of a circuit because analog/mixed-signal design technologies comprise so many different devices with various parameter specification windows and model variants. However, only reasonable combinations of device model variants are useful and, traditionally, designers must define and limit manually feasible corners. According to Cadence, Virtuoso NeoCircuit DFM avoids these limitations.
Thomas Ramsch, Director Design Support at X-FAB said, "Based on its proven merits, we selected Virtuoso NeoCircuit DFM to help ensure we deliver the best quality for our customers. It enables X-FAB to better analyze the robustness of our analog IP, minimize parametric sensitivities, and tweak the design process for maximum yield."
In addition to the traditional Monte-Carlo analysis – which has been supported on X-FAB's 0.6-µm technologies and also will be available for 0.35-µm process technology by the end of the year – Virtuoso NeoCircuit DFM combines the features of a parameter synthesizer, or optimizer engine, in a closed loop with a yield improvement algorithm. Virtuoso NeoCircuit DFM uses a tool-based automated design centering methodology to improve yield by tuning the average-sized device for manufacturing process tolerances and operating condition environmental variations. It enables quick intuitive use through all optimization steps supported by the Virtuoso NeoCircuit DFM toolbox top-down workflow.
A powerful built-in visualization tool helps designers judge the sizing results based on a sensitivity analysis, and track all optimization steps during design space exploration. Designers gain a better understanding of how much a circuit's performance or goal function is impacted by variations in device parameters, and can find out what causes circuit limitations. For a certain circuit topology, designers can create universal constraint-based device relationships and circuit goal functions within the Virtuoso NeoCircuit DFM workflow that are re-usable for new design tasks. This feature also speeds the cell development cycle and minimizes the design effort.
Go to the X-FAB Semiconductor Foundries AG website to find additional information.