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An Initiative Towards Open Network-on-Chip Benchmarks

Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for Networks on Chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability.

For performance benchmarking it describes requirements and features for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric.

This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite.

Read the entire on the OCP International Partnership (OCP-IP) website.

A Layered Approach to NoC

The challenge of on-chip communication traffic is presently compounded in two ways: First, use of multiple processors and cores with single or multiple memories in system-on-chips (SOCs) are driving the need for a lower cost, easier to design and more elegant on chip communication solution. Second, existing bus-based interconnect architectures and techniques are proving to be non-scalable, unable to meet leading edge complexity and performance requirements. Both issues create unprecedented challenges in achieving timing closure and meeting the power requirements of today’s most sophisticated consumer, communications and computing applications.

Fortunately, new approaches have emerged, most notably Network on Chip (NoC), to allow efficient and high-performance on-chip communications for complex SOC designs. The NoC has a key advantage in that it uses fewer global wires than a bus and those wires that it uses are point-to-point. This allows a NoC to operate with half the power of a bus at the same operating frequency while offering over three times the operating frequency. System bandwidth is easily adjusted by increasing the width of NoC links and switches. Scalability of a NoC supports SOCs comprising hundreds of IPs with concurrent support for multiple IP protocols. However, even within the emerging NoC space, there are differing approaches that meet these basic requirements.

Read the entire article from Arteris SA on SOCcentral.

Synchronous Interconnect is Hitting the Wall

Ask SOC designers to name the biggest problems they face and, invariably, timing closure and power dissipation are at the top of the list. There are several reasons for the existence of these problems, including increasing design and process complexity, but one of the major problems is the use of clocked, synchronous buses to connect the various IP cores on a chip. It is apparent that synchronous interconnect and the global clocking methodology needed to support it is just not able to handle the types of SOC designs typically done at 130nm and below, and no amount of increased clock frequencies or multicore architectures will remedy the situation. It’s time to move to clock-less, self-timed interconnect to enable communication between the IP blocks on a chip. A self-timed interconnect fabric on an SOC, with the right tool suite to generate the complex circuitry, offers many design and performance advantages to the chip designer beyond just power saving and timing-closure acceleration.

Read the entire article from Silistix, Inc. on SOCcentral.

On-Chip Interconnects for Multi-Core Chips: A Software Perspective

Portable and distributed multi-media applications are driving an ever increasing demand for computational performance at acceptable power consumption levels, both at the client and the infrastructure sides. At the same time, the software content driven by functional requirements is constantly increasing and is already in the millions of lines of code in some devices. Parallel processing offers power consumption relief but it brings new challenges as well. A number of multi-core chips are already in the market and with shrinking silicon geometries we will see an increasing number of (homogenous and heterogeneous) cores per chip.

Most of the current dual-core chips have shared memory and a bus. While the bus and shared memory architecture is quite simple from a programming perspective (the cores can easily exchange data), the bus will become a bottleneck as the number of cores increase. We can, therefore, expect to see more and more types of interconnects, such as multi-level buses, crossbars, point-to-point, mesh, network-on-chip, etc., in different logical structures, as well as non-uniform memory architectures much like they have been used at the board level and beyond for a long time. Effective interconnect systems are, or will become, as important for multi-core chips as efficient caches for a single processor.

Read the entire article from PolyCore Software, Inc. on SOCcentral.

Networks on Chip for Managing On-Chip Communications

Networking has been proven in the computer systems arena to be an extremely effective means of managing communications among any collection of distributed systems that need some level of inter-communications. As more different types of functions, in the form of intellectual property (IP) blocks, are integrated into a single system on chip (SOC), a similar need for managing communications among the potentially very different needs of these functions becomes critical.

Approaches used to date have relied on some form of shared resource, typically derived from the shared bus architectures that are common to all processors, regardless of their specific processing characteristics. Due to limitations on the number of resources that can effectively share such a "bus," the difficulties of implementing these shared resources in deep sub-micron process technologies, the disparate nature of communications traffic imposed by the integration of different functions, and other issues, a new approach to managing the communications on chip must be found.

Fortunately, new approaches have emerged, among them Network on Chip (NoC) to allow efficient and high-performance on-chip communications for complex SOC design. The NoC advances traditional bus-based techniques to manage the increasingly on-chip communications requirements of SOCs containing tens or even hundreds of IP blocks.

Read the entire article from Arteris SA on SOCcentral.