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SystemVerilog Assertions in an SOC Environment

Verification tools and methodologies have both evolved and undergone revolutionary changes, and both are equally as important. Without a doubt, simulators and support tools have evolved to keep pace with the incremental requirements, primarily increasing designs size. But it is the "revolutions" that provide the significant increase in productivity necessary to stay abreast of Moore’s law. While the hoopla around Moore’s law has traditionally been around advances in semiconductor technology, it is worth noting that whatever you build or want to build has to be verified (unless of course all you are going to build is memory).

Complex SOC designs can be implemented by acquiring third-party intellectual property (IP), a divide and conquer approach within development teams, and, of course, by adding more designers. Verification, on the other hand, must deal with the large (well, humungous) designs as a whole. This burden falls on the underlying verification tools and associated methodologies that must be able to "simulate" a model of the design, often at different levels of abstraction, e.g., register transfer level (RTL), gate, etc. Fortunately, assertion-based verification enables a revolutionary methodology change that addresses this ever-increasing burden by adding observability (result checking) and testing (development of actual tests) into the verification environment.

Read the entire article from Novas Software, Inc. on SOCcentral.

Coding Guidelines for an Effective Methodology for SystemVerilog Assertions Local Variables

SystemVerilog Assertions (SVA) constitute a major language feature of the IEEE Std. 1800-2005 SystemVerilog standard. Local variables are a powerful component of SVA that allow the sampling and manipulation of data in a property or sequence without requiring the property writer to define auxiliary state machines to model additional behavior when composing the property or sequence.

During assertion evaluation, local variables dynamically allocate storage to hold the sampled data for later reference. Theoretically, this unique capability enhances the expressiveness of the language allowing SVA to model extra temporal behavior concisely, which otherwise requires auxiliary modeling or obscure rewriting to specify the desired behavior. For example, local variables are often used to express a class of properties associated with data integrity—such as a data packet properly traversing through a design block. However, the enhanced expressiveness of SVA also adds considerable complexity to the assertion and its evaluation.

In simulation for certain local variable use patterns, the amount of dynamic storage required to remember the sampled data can be huge and essentially has no upper limit, resulting in increased memory use and potential performance degradation. With formal verification, local variable constructs are compiled into extra sequential elements in the checker; the increased checker complexity thus reduces the effectiveness of the underlying formal algorithms considerably. Unfortunately, these added complexities may prevent users from applying local variables effectively.

A set of coding guidelines and a methodology for efficient SVA local variable will help you take advantage of the expressiveness of SVA local variables while avoiding the potential pitfalls that would result in reduced performance and capacity

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Error Checking and Functional Coverage with SystemVerilog Assertions

Hundreds, if not thousands, of articles have been written to discuss the “verification crisis” for system-on-chip (SOC) designs. The crisis is real: many studies have shown that two or three very expensive silicon iterations are the norm today. Of the many techniques and methodologies that have arisen to improve this situation, few have had more impact than assertion-based verification.

Assertions are, quite simply, expressions of design intent. As architects write chip and system specifications, they make many assumptions about the functionality. As designers write RTL, they develop implementation-level beliefs on how the design should operate and expectations about how neighboring blocks will communicate. Verification engineers document intended and unintended design behavior as part of developing a test plan.

All of the different elements of design intent can be captured with assertions, starting very early in the project schedule. The traditional test plan is replaced by a more comprehensive verification plan identifying which assertions should be written. The architects, designers, and verification engineers should all contribute to this plan. As the assertions are specified, links can be added to tie the plan to the verification results.

There are many methods for specifying assertions, including checker libraries, the VHDL assertion construct, Property Specification Language (PSL), and various proprietary formats. This article focuses on SystemVerilog since this standard language includes sophisticated assertion constructs that have gained wide acceptance. As will be discussed in later sections, these constructs also support functional coverage specification.

Read the entire article from Cadence Design Systems, Inc. on SOCcentral.