What is the difference between VHDL and SystemVerilog? John Aynsley from Doulos compares these two language standards.
SystemC versus SystemVerilog
What is the difference between SystemC and SystemVerilog? This video includes a brief description of these two EDA language standards.
Coding Guidelines for an Effective Methodology for SystemVerilog Assertions Local Variables
SystemVerilog Assertions (SVA) constitute a major language feature of the IEEE Std. 1800-2005 SystemVerilog standard. Local variables are a powerful component of SVA that allow the sampling and manipulation of data in a property or sequence without requiring the property writer to define auxiliary state machines to model additional behavior when composing the property or sequence.
With formal verification, local variable constructs are compiled into extra sequential elements in the checker; the increased checker complexity thus reduces the effectiveness of the underlying formal algorithms considerably. Unfortunately, these added complexities may prevent users from applying local variables effectively.
A set of coding guidelines and a methodology for efficient SVA local variable will help you take advantage of the expressiveness of SVA local variables while avoiding the potential pitfalls that would result in reduced performance and capacity
Error Checking and Functional Coverage with SystemVerilog Assertions
Hundreds, if not thousands, of articles have been written to discuss the “verification crisis” for system-on-chip (SOC) designs. The crisis is real: many studies have shown that two or three very expensive silicon iterations are the norm today. Of the many techniques and methodologies that have arisen to improve this situation, few have had more impact than assertion-based verification.
There are many methods for specifying assertions, including checker libraries, the VHDL assertion construct, Property Specification Language (PSL), and various proprietary formats. This article focuses on SystemVerilog since this standard language includes sophisticated assertion constructs that have gained wide acceptance. As will be discussed in later sections, these constructs also support functional coverage specification.
SystemVerilog includes a number of enhancements to the Verilog language that are useful for FPGA design. Synthesis tools from FPGA vendors and EDA tool vendors enable SystemVerilog designs to be described using easier-to-understand styles and higher levels of abstraction than were possible in Verilog, speeding up the coding process and easing reuse. This article looks at how synthesisable SystemVerilog can be written for various functional blocks commonly used in FPGAs. An example design based around a generic bus with multiple arbitrated masters and multiple slaves is used to illustrate synthesisable coding styles. Some of the techniques described here have been borrowed from VHDL while others are only possible with SystemVerilog.
