February 17, 2005 -- Device and parasitic extraction has always been an issue at some level. Analog designs are handcrafted and are more prone to signal flaws than are digital designs. Therefore, they have a greater impact on full-chip power and electrical behavior. At larger process technologies, such as 250 nm, engineers could handle device extraction with an LVS (layout-versus-schematics) tool using an assumptive method of measuring physical parameters. They could also perform parasitic extraction by using tools employing simple cell characterization at the gate level. However, in the nanometer era, with its advanced functions, complicated interconnect, mixed-signal components, and restricted on-chip real estate, assumptive parameter measurement, and gate-level extraction become insufficient. Designers need more extensive data to perform accurate simulation and to solve the ever-increasing parasitic effects that can cause chip failures, such as noise, faulty timing, and reduced power and signal integrity.
By Brian Marshall. (Marshall is a technical-marketing engineer in the Calibre Design to Silicon Division of Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.