March 11, 2005 -- Power supply noise and related issues have become critical for designs at 90nm and below due to the combination of several factors. Timing slowdown and functional failures are becoming common in these designs due to the power grid noise. However, physical design and verification methodologies have not sufficiently evolved to adequately address these power supply noise issues.
Planning, resource allocation, and design of a chip's power supply, which includes package, decoupling capacitance, and power grid network, have to be done in a holistic manner along with sign-off quality verification and analysis. Designers need techniques to reduce the dynamic voltage drop (DvD) in a design and its impact on timing and functionality, and they need to adopt a power aware physical design methodology.
By Aveek Sarkar. (Sarkar is a senior product engineer at Apache Design Solutions.)
This brief introduction has been excerpted from the original copyrighted article.