Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2005: Saturday, October 25, 2014
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (160 Entries)
Reaching Down: 32-bit Processors Aim for 8 Bits  by EDN Magazine

February 17, 2005 -- A new breed of low-cost, 32-bit devices is targeting the healthy market share that 8- and 16-bit devices have exclusively supported. According to Isuppli's 2004 microcontroller-unit-market forecast, 8-bit devices account f ... read more

Getting to Silicon: Accuracy Requirements of Nanometer Designs  by Mentor Graphics Corp. in EDN Magazine

February 17, 2005 -- Device and parasitic extraction has always been an issue at some level. Analog designs are handcrafted and are more prone to signal flaws than are digital designs. Therefore, they have a greater impact on full-chip power a ... read more

How to Create Beam-Forming Smart Antennas Using FPGAs  by Altera Corp. in EE Times Embedded

February 17, 2005 -- There are two constants in the cell-phone business: demand for higher data rates and demand for greater user capacity. Both depend on a unique factor known as spectrum efficiency, the ratio of information bits transmitted ... read more

Coverage Is the Heart of Verification   by Synopsys, Inc. in eeDesign (EE Times EDA News)

February 14, 2005 -- Every design verification technique requires coverage metrics to gauge progress, assess effectiveness, and help determine when the design is robust enough for tapeout. At every step of the way and with every bug-finding te ... read more

IP Reuse Requires a Verification Strategy   by Denali Software, Inc. in eeDesign (EE Times EDA News)

February 08, 2005 -- Intellectual property (IP) reuse has long been touted as one of the keys to enabling today's massive SoC designs. The concept of reuse seems simple and easy in theory, but there are a number of obstacles that design and ve ... read more

Microelectronics Applications Require the Right Stacked-Memory Packaging Architecture  by Amkor Technology, Inc. in EDN Magazine

February 3, 2005 -- Increasingly, memory chips—in combinations of all their flavors, including DRAM, SRAM, and flash—are at the forefront of microelectronics end-product functions. This scenario is true for cell-phone handsets, broadband devices ... read more

Third-Party IP: A Shaky Foundation for SOC Design  by EDN Magazine

February 3, 2005 -- Lawyers have labeled reusable design blocks, or cores, as IP (intellectual property), despite the fact that most electronics designers use IP to mean Internet Protocol, and most engineers prefer to describe such product ... read more

S-parameters and Digital Circuit Design  by Intel Corp. in EDN Magazine

February 3, 2005 -- In the days of relatively slow 66-MHz buses, designers could ignore signal-integrity effects without problem, certainly for small boards. Similarly, they didn't have to know about S-parameters (scattering parameters), long us ... read more

How Memory Architectures Affect System Performance  by Rambus, Inc. in eeDesign (EE Times EDA News)

January 31, 2005 -- Since the mid-1990s, memory technologies have mostly been named according to how fast they run. A PC100 SDRAM device would operate at a 100MHz data rate, PC133 at a 133MHz data rate, and so on. While variations on this bran ... read more

Sorting Data in Two Clock Cycles  by EE Times Embedded

January 27, 2005 -- Sorting data efficiently is a problem that many mathematicians have investigated by trying to minimize the complexity of algorithms. The need for efficiency grows with the number of elements or the number of repetitions in ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Executive
Viewpoint

Deep Semantic and Formal Analysis


Dr. Pranav Ashar
CTO, Real Intent

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.563  0.140625