| An IP Storm? by EDN Magazine |
June 23, 2005 -- The continuously increasing number of components that silicon vendors are fitting onto a single chip has been driving the need for a correlating increase in developer productivity. Designers are increasingly acquiring IP (inte ... read more |
| Equivalency Checking Verifies Sequential Changes by Calypto Design Systems, Inc. in eeDesign (EE Times EDA News) |
June 20, 2005 -- Sequential equivalence checking gives designers
another functional verification option. By proving equivalence between designs
with sequential differences, all previous functional verification investment is
leveraged acr ... read more |
| A Thermal-Aware IC Design Methodology by Gradient Design Automation, Inc. in eeDesign (EE Times EDA News) |
June 13, 2005 -- Technology scaling to 90nm and below brings higher performance and higher levels of on-chip functional integration. This scaling, however, has brought with it a variety of new or exacerbated issues, such as higher current and ... read more |
| Filters in a Nutshell: Spreadsheet Promotes Intuitive Feel by Cypress MicroSystems, Inc. in EDN Magazine |
June 9, 2005 -- When almost any electronic system passes a certain level of complexity, it requires some sort of filtering - often several types. However, many designers with a predominantly digital background may hesitate to tackle analog fil ... read more |
| Top-down Approach Speeds Mixed-Signal design by Freescale Semiconductor, Inc. in eeDesign (EE Times EDA News) |
June 6, 2005 -- Mixed-signal verification lies at the heart of a designer's constant battle between silicon accuracy and shorter development time. Silicon accuracy, essential to meeting performance parameters, is typically achieved in the desi ... read more |
| In Search of an ESL Design Methodology by Chip Design Magazine |
June 1, 2005 -- The last two years were a period of struggle for electronic system level (ESL). Numbers were down, confusion was up, and a record number of users started building their own internal ESL CAD tools. The only good news was that th ... read more |
| Navigating the Silicon Jungle: FPGA or ASIC? by Chip Design Magazine |
June 1, 2005 -- As if designing today’s chips weren’t challenging enough, engineers now have new considerations to balance when choosing the best way to implement their designs. High-end field-programmable gate arrays (FPGAs) are growing in de ... read more |
| Advantages Abound for a Conversion-Free, Low-Cost Path to Volume Production by Xilinx, Inc. in Chip Design Magazine |
June 1, 2005 -- As the semiconductor industry moves toward smaller process nodes, the cost of developing an ASIC is increasing exponentially. For example, designing a 90-nm ASIC requires an up-front NRE cost in excess of $1M. In addition to th ... read more |
| A Tale of Two Languages: SystemC and SystemVerilog by Cadence Design Systems, Inc. in Chip Design Magazine |
June 1, 2005 -- Standard system languages, such as SystemVerilog and SystemC, promise to arm system architects, design engineers, and verification engineers with essential capabilities. Along with Verilog, these languages offer complementary c ... read more |
| IP Reuse Gets a Reality Check by VSI Alliance (VSIA) in Chip Design Magazine |
June 1, 2005 -- Business drivers, such as improved time to market and better resource utilization, have become a significant factor in the system-on-a-chip (SoC) development process. The decisions that affect market windows and resource utiliz ... read more |
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