May 1, 2004 -- As integrated circuits (ICs) continue to grow in size and complexity, designers are faced with the challenge of keeping track of exponential increases in data volume and design complexity. The move to hierarchical design styles, in conjunction with the incorporation of large blocks of functional units of intellectual property (IP), is providing only a limited ability to stretch the existing RTL tools to meet today’s demands. Current tools max out at 40 millions, give or take - far short of the promised real estate at 90 nanometers, let alone 65 nanometers and below. Not surprisingly, people are now looking for the next breakthrough in design productivity and are thinking it may be in the electronic system-level (ESL) tools.
The key here is to move to the next level abstraction, to start at the architectural level and refine down from there. The tools to support this move will have to simultaneously address large, high-level blocks such as processors and large peripherals, and the gate-level detail of an address decoder. In addition, the tools will need to handle the integration of hardware and software, since one of the parameters for optimization is system throughput versus power consumption.
By Tets Maniwa, Chip Design Magazine Editor-in-Chief
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Chip Design Magazine website.