October 01, 2004 -- The entire electronics industry's economic structure is based on getting ever more complex silicon at ever lower prices. The problems in silicon yield ramp are seriously threatening this model. Yield ramp is taking longer with each successive process generation, while the cost of low yield grows. Given the current trends, remarkably, most nanometer-scale ICs will not reach nominal yield in their lifetimes.
This article describes the underlying problem, the limitations with existing approaches, and a proven methodology to accelerate yield ramp. The methodology is based on a new category of diagnostics software — yield diagnostics — that was developed specifically for manufacturing yield ramp and yield learning applications. The methodology utilizes volume yield diagnostics to identify the most critical design-process yield issues combined with precision yield diagnostics to accurately locate root cause defects.
By Paul Estrada. (Estrada is the general manager of Cadence Design Systems' Encounter Test business unit.)
This brief introduction has been excerpted from the original copyrighted article.