| How Statistical Sensitivity Makes Designs Manufacturable by in eeDesign (EE Times EDA News) |
December 09, 2004 -- Statistical sensitivity is a key measure used in design for manufacturability. It is defined as the slope of a yield factor histogram. Reducing statistical sensitivities increases product yield and makes for a more manufac ... read more |
| Accurate Power-Analysis Techniques Support Smart SOC-Design Choices by Synopsys, Inc. in EDN Magazine |
December 7, 2004 -- As power consumption becomes increasingly critical for both portable and nonportable applications, accurate techniques for predicting an SOC's (system on chip's) power have become essential. Designers need to know, for exam ... read more |
| The Why, Where and What of Low-Power SoC Design by Cadence Design Systems, Inc. in eeDesign (EE Times EDA News) |
December 02, 2004 -- Reducing on-chip power consumption has become a critical challenge for the nanotechnology era. The traditional trade-offs between performance and area are now being compounded by the addition of power into the equation.
... read more |
| Generate Those Low Voltages Needed For FPGA-Based Boards by Intersil Corp. in Electronic Design Magazine |
November 29, 2004 -- It's now common for FPGA-based boards to require as many as four or five different low-voltage supplies to power the various components. First it was 3.3 V, then 2.5 V, 1.8 V, 1.5 V, and now 1.2 V. Each new FPGA generation ... read more |
| SiP Really Packs It In by in Electronic Design Magazine |
November 29, 2004 -- Shorter development times and and cost-effective miniaturization make for an unbeatable combination. Those just happen to be the attributes of the quickly rising system-in-a-package (SiP) technology. In a straightforward m ... read more |
| Semiconductor Options for Real-Time Signal Processing by Texas Instruments, Inc. (TI) in EDN Magazine |
November 25, 2004 -- If a universal semiconductor component existed that could allow engineers to realize every real-time-signal-processing system with optimum price, performance, power and function, then selection would be automatic. However, ... read more |
| Watch Your Step: IC Technology and Tools Face Economic Hurdles by EDN Magazine |
November 25, 2004 -- As semiconductor technology has progressed from 2 microns, to today's 90-nm processes, and on to 65 nm, the number of design elements that have gone from being fixed or "given" to being variable has been increasing. In man ... read more |
| "Wrap" Your Cores to Enable SoC Test by ARM in eeDesign (EE Times EDA News) |
November 24, 2004 -- Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies and system-on-chip (SoC) ... read more |
| Use Macrocells to Automate Analog/Mixed-Signal Design by Tanner EDA in eeDesign (EE Times EDA News) |
November 19, 2004 -- Analog and mixed-signal design are often regarded as representing significant bottlenecks in system-on-chip (SoC) design. A manually intensive process that has proven difficult to automate, the belief is that analog design p ... read more |
| Solve the Issues Associated with Analog-To-Digital IP Integration by LTRIM Technologies, Inc. in Electronic Design Magazine |
November 15, 2004 -- The huge increase in variety and number of ways
people interact with electronic communications systems is no secret. More cell
phones, wireless computers, and other multifunction, media-rich products such as
PDAs, MP ... read more |
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