| Accelerating Algorithms in Hardware by Altera Corp. in EE Times Embedded |
January 20, 2004 -- When you're trying to get the best performance out of your code, what do you do? Optimize your algorithms, use look-up tables instead of algorithms, turn everything into native-word sizes, use registered variables, unroll l ... read more |
| HP Adopts OpenAccess for 90nm Flow by Hewlett-Packard in Electronic Engineering Times (EE Times) |
January 16, 2004 -- To help CAD development teams meet this challenge of maximizing productivity, the OpenAccess Coalition has launched an industry-wide effort to provide true open interoperability across IC design tools through an open, standar ... read more |
| Access, Navigation are Design Keys to Easy Circuit Editing by in Electronic Engineering Times (EE Times) |
January 15, 2004 --Though the value of circuit editing is well-established, its benefits often are not fully realized because design and manufacturing practices do not adequately consider the circuit-edit process. Circuit edit -- the practice of ... read more |
| Designing with Hard Power Constraints by IBM Corp. in Electronic Engineering Times (EE Times) |
January 15, 2004 -- In high-performance 90-nanometer designs that are communications-intensive, power has become a hard constraint, and not just in battery-powered devices. High-performance computing chips, broadband processors and networking si ... read more |
| Design-for-Manufacturing Demands New Infrastructure by Mentor Graphics Corp. in Electronic Engineering Times (EE Times) |
January 15, 2004 -- Until recently, predicting IC yield was fairly straightforward: If you could manufacture each structure, you could manufacture the entire chip. The design that was drawn was the one printed on the wafer. The only insight desi ... read more |
| Islands in the Power Management Storm by Virtual Silicon Technology, Inc. in Electronic Engineering Times (EE Times) |
January 15, 2004 -- A perfect storm of forces-mobility, process technology and system-on-chip complexity-are combining to create a tsunami of challenges for SoC designers who need to manage dynamic power consumption and static leakage at 130- an ... read more |
| Modeling In-die Process variation with Accuracy by Synopsys, Inc. in Electronic Engineering Times (EE Times) |
January 15, 2004 -- As technology nodes shrink to 90 nanometers and below, chips become much more difficult to manufacture. In-die process variations increase substantially at 90 nm — even more at 65 nm. If these effects are not modeled accurate ... read more |
| Process Shrinks Alone Won't Cut It by Texas Instruments, Inc. (TI) in Electronic Engineering Times (EE Times) |
January 15, 2004 -- Many product road maps show process migration years down the road as a fait accompli. A process shrink alone, however, will not enable developers to keep pace with Moore's Law. Running a longer pipeline 40 percent fa ... read more |
| Using RTL Floorplanning to Budget Nanometer Designs by InTime Software, Inc. in Electronic Engineering Times (EE Times) |
January 15, 2004 -- Today's nanometer technology design activity provides a means to capture functional intent using a top-down methodology. A key factor in successful timing closure is setting good physical and timing constraints as the design ... read more |
| Non-Linear Effects in Low-Power Sub-100nm Designs by Magma Design Automation, Inc. in Electronic Engineering Times (EE Times) |
January 15, 2004 -- Advanced process nodes are leakier than the larger-geometry processes and exhibit voltage and temperature nonlinearity and instability. Techniques are being developed to control leakage power, decrease overall power consumpti ... read more |
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