| Design Great Interconnects By Treating FPGAs Like Software by TEK Microsystems, Inc. in Electronic Design Magazine |
October 18, 2004 -- The potent combination of FPGA processing and switch-fabric interconnect offers systems designers dramatic increases in both processing throughput and scalable bandwidth¾within existing volume and power constraints. However ... read more |
| Architectural Advances Propel FPGAs Into High-End ASIC Turf by in Electronic Design Magazine |
October 18, 2004 -- Finer features and architectural enhancements let the latest-generation FPGAs deliver higher gate counts and application-targeted resources to implement complex systems-on-a-chip.
The rules of the ASIC game are changin ... read more |
| Comparing Debugging Methods for Embedded Software by STMicroelectronics in EDN Magazine |
October 14, 2004 -- An SOC (system on chip) includes many
components, such as processors, timers, interrupt controllers, buses, memories,
and embedded software. It is a complete system that designers a few years back
would have assembled ... read more |
| Process Improvements for System on Chip Developments by Parama Networks, Inc. in Electronic Engineering Times (EE Times) |
October 11, 2004 -- The development of system-on-chip products requires some rethinking of the development process. The SoC designs for transport silicon for the telecommunications market carry with them a new degree of complexity that can str ... read more |
| Integrating High Speed Serial Transceivers into an FPGA by Altera Corp. in Electronic Engineering Times (EE Times) |
October 11, 2004 -- The acceptance of serial standards and protocols like PCI Express, Serial Rapid I/O and SerialLite will increase the use of high-speed serial transceivers with clock and data recovery (CDR). These transceivers, once offered ... read more |
| Designing an Optimal Wireless SoC by GCT Semiconductor in Electronic Engineering Times (EE Times) |
October 11, 2004 -- The semiconductor industry is expected to provide complete and optimal system solutions, including silicon, firmware, external components, board layout (in the form of Gerber files) and even, in some cases, man-machine inte ... read more |
| Taking GALS to 65-nm Designs by Fulcrum Microsystems, Inc. in Electronic Engineering Times (EE Times) |
October 11, 2004 -- Industry wisdom has it that the winning designs at 65 nanometers will be the ones that master the "superintegration" of many logic blocks on a chip. For system-on-chip designers, this opens up the possibility of dramaticall ... read more |
| IP Reuse Simplifies SoC Design, Verification by Mentor Graphics Corp. in Electronic Engineering Times (EE Times) |
October 11, 2004 -- Larger, more-complex digital designs demand inventive techniques and tools that simplify the design and verification process. This is a response to both design complexity challenges and the new opportunities of increased si ... read more |
| Restoring Predictability in SoC Integration by ReShape, Inc. in Electronic Engineering Times (EE Times) |
October 11, 2004 -- Of the more than 1,000 IC projects reviewed in a March study by Numetrics, Inc., 85 percent missed their target delivery date. Just as alarming, the average project overran its schedule by a factor of 53 percent. Numbers li ... read more |
| RF Integration: Changing the Face of Test by Agilent Technologies, Inc. in Electronic Engineering Times (EE Times) |
October 11, 2004 -- In the wireless world, the only constant is change. With the push for single-chip implementations of wireless products, new radio architectures are emerging. This can be seen in mobile phones, wireless-LAN and Bluetooth app ... read more |
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