| How Tensilica Verifies Processor Cores by Tensilica, Inc. in eeDesign (EE Times EDA News) |
April 4, 2003 -- Millions of gates on an SoC lead to dozens, hundreds, or thousands of RTL blocks that all require the creation of verification test suites. To crawl out of the SoC design-verification quagmire and profitably exploit those millio ... read more |
| Current Challenges Dictated by Today's IC Packaging Trends by Amkor Technology, Inc. in Solid State Technology |
April 1, 2003 -- With all the attention given to wafer processing, IC advances, and microelectronics end products, we tend to lose sight of the fact that IC packaging is also being pushed to a higher level of sophistication. There is an increasi ... read more |
| Why You Need RTL Virtual Prototyping by Cadence Design Systems, Inc. in eeDesign (EE Times EDA News) |
March 28, 2003 -- Out of all these challenges chip designers face, timing closure has probably been the number one digital IC implementation challenge since at least 1990. What's really going on here? What's fundamentally the issue?
For di ... read more |
| Diagnostics for Design Validation by IBM Corp. in EE Times Embedded |
March 3, 2003 -- Writing software to verify the design of a silicon device is quite different from other types of embedded software development. This article introduces the subject of post-silicon validation and provides techniques for the softw ... read more |
| Simple Techniques for Making Verification Reusable by Integre Technologies LLC in eeDesign (EE Times EDA News) |
March 21, 2003 -- Writing reusable verification code takes extra effort and requires engineers to follow some basic guidelines. In many respects, this is no different than writing reusable software modules or maintainable RTL hardware modules. E ... read more |
| Merged-Logic-Type Embedded DRAM Suits High-Performance SoCs by NEC Electronics America, Inc. in Electronic Engineering Times (EE Times) |
March 19, 2003 -- To push access times toward those of SRAM while achieving much higher densities, embedded DRAM needs a structure that differs from both commodity DRAM and conventional embedded DRAM. The challenge is to develop a semiconductor ... read more |
| Mobile Generation Needs FRAM by Texas Instruments, Inc. (TI) in Electronic Engineering Times (EE Times) |
March 18, 2003 -- In the late 1990s, after more than a decade of ferroelectric-memory development, several companies succeeded in the high-volume production of low-density (less than 1-Mbit) ferroelectric RAM. These nonvolatile memories have an ... read more |
| Speed with Flexible Design Critical to Embedded DRAM for SoCs by IBM Corp. in Electronic Engineering Times (EE Times) |
March 18, 2003 -- The incorporation of embedded dynamic random-access memory (DRAM) in a system-on-chip (SoC) environment presents some unique challenges. IBM has developed an embedded DRAM solution for application-specific integrated circuit (A ... read more |
| Manufacturability, Scalability: a Critical Test of SoC Memories Strategies by in Electronic Engineering Times (EE Times) |
March 18, 2003 -- Since no one questions the performance benefits of embedding large memory blocks in SoCs, the only major issues to address are cost, time to market and design risk. Memory structures that are highly manufacturable and scalable ... read more |
| Nonvolatile Memories for 90-nm SoC and Beyond by in Electronic Engineering Times (EE Times) |
March 18, 2003 -- In many SoC applications, it is desirable to store code and data in a non-volatile memory to maintain the state of the system even in the power-off state. The most flexible solution is to embed a Flash EEPROM into the SoC, in w ... read more |
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