| Philips' Silicon Hive to develop IP cores by in Electronic Engineering Times (EE Times) |
March 14, 2003 Eindhoven, Netherlands -- "Philips Research is spinning out a reconfigurable computing architecture it has kept under wraps since the early 1990s to an incubator company called Silicon Hive, which will develop and license synthesi ... read more |
| Shifting from Functional to Structured Techniques Improves Test Quality by Synopsys, Inc. in Electronic Engineering Times (EE Times) |
March 10, 2003 -- "It is becoming clear that functional testing of integrated circuits, the most widely used and oldest method in the semiconductor industry has reached the limits of its effectiveness. Functional Test methods rely on a of pre-ex ... read more |
| What Designers Need to Know about Structural Test by LTX-Credence Corp. in eeDesign (EE Times EDA News) |
March 6, 2003 -- "Facing both increasing competitive pressures and rising device complexity, integrated circuit (IC) companies are looking for more effective strategies able to speed delivery to market of higher quality products. Until now, manu ... read more |
| Linking Synthesis with DFT Key for Network Switch ICs by Get2Chip, Inc. in Electronic Engineering Times (EE Times) |
March 4, 2003 -- "As the challenges of network execution time reach new heights, the question of integrating synthesis and design-for-test (DFT) in the fabrication of high density networking devices merits reassessment.
"The challenges th ... read more |
| Pre-Configured DFT Structures Can Simplify ASIC Design, Verification by NEC Electronics America, Inc. in Electronic Engineering Times (EE Times) |
March 3, 2003 -- "The integration of test capabilities into the underlying structure of an ASIC eliminates the extra design-for-test (DFT) steps that complicate conventional front- and back-end design flows. Rather than distracting from the prim ... read more |
| Fault Coverage Founders on Speed by Mentor Graphics Corp. in Electronic Engineering Times (EE Times) |
March 3, 2003 -- "Regardless of the test methodology employed, the goal of manufacturing test is to identify, or screen out, defective devices before they are embedded into a system or shipped to the end customer. More effective (or higher-quali ... read more |
| Bandwidth Match Avoids I/O Snarl by Agilent Technologies, Inc. in Electronic Engineering Times (EE Times) |
March 3, 2003 -- "Scan is the most general and pervasive digital structural-test technique, one that has been a standard in the industry for years. However, scan-design methodologies have not improved in all that time. The traditional methodolog ... read more |
| Creating Value Through Test by Philips Semiconductors NV in Electronic Engineering Times (EE Times) |
March 3, 2003 -- "Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the customer. In this paper, we show that techniques an ... read more |
| Moving DFT to RTL Overcomes Test Vector Issues by Atrenta, Inc. in Electronic Engineering Times (EE Times) |
March 3, 2003 -- "In the IC design flow, design-for-test is often an afterthought. First, the design is coded, then simulated, then synthesized, and only after all that - usually months into the design cycle - it's handed over to a test team to ... read more |
| Analog Circuits Need More Than Just DFT Methods by PolarFab, Inc. in Electronic Engineering Times (EE Times) |
March 3, 2003 -- "Digital design is, of necessity, performed at a very high level of abstraction. When dealing with millions to hundreds of millions of transistors, working at the transistor level is completely impractical. Designers of digital ... read more |
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