| Techniques to Make Clock Switching Glitch Free by Altera Corp. in eeDesign (EE Times EDA News) |
June 26, 2003 -- With more and more multi-frequency clocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a clock line while the chip is running. This is usually implemented by ... read more |
| Metal Layers a Key to Interconnect Delay? by in Electronic Engineering Times (EE Times) |
June 23, 2003 -- Interconnect delay has moved to the forefront as the limiting factor in IC performance, replacing a longtime concern with switching speeds. That concern was prompted by advancements in deep-submicron process geometries that have ... read more |
| SoC Interconnect Crisis: Path Delays Cancel Speed Increase by in Electronic Engineering Times (EE Times) |
June 23, 2003 -- An integrated circuit at 0.25-micron design rules contains about 800 meters of wire interconnect, draining 50 percent of the power consumed by the circuit. When 0.01-micron chips emerge, they will typically have a total of 5 km ... read more |
| COT Design Path Eyes Interconnect Crunch by Procket Networks, Inc. in Electronic Engineering Times (EE Times) |
June 23, 2003 -- Designers of internetworking products face a number of challenges that dictate choices in chip design methodologies. The Internet is growing slightly faster than the formidable Moore's Law. Packet-processing requirements get mor ... read more |
| Needed: High-level Interconnect Methodology for Nanometer ICs by LSI Corp. in Electronic Engineering Times (EE Times) |
June 23, 2003 -- Decades of remarkable microelectronic technology development has largely benefited from transistor scaling. The smaller feature size allows both higher chip density and higher transistor performance simultaneously. However, the ... read more |
| Custom SoC Designers Must Consider Interconnect Effects by Toshiba America Electronic Components, Inc. (TAEC) in Electronic Engineering Times (EE Times) |
June 23, 2003 -- Digital integrated circuit interconnects have characteristics that must be considered as an integral part of the design process. SoC designers can't be fully decoupled from the manufacturing process. Interconnect and related sig ... read more |
| Signal Integrity a Challenge in IC Design by Magma Design Automation, Inc. in Electronic Engineering Times (EE Times) |
June 23, 2003 -- Designing ICs on 0.13-micron and smaller process technologies poses tremendous challenges. The number of silicon failures caused by signal integrity problems is on the rise because existing design tools and methodologies cannot ... read more |
| Using "Empty Space" for IC Congestion Relief by in eeDesign (EE Times EDA News) |
June 19, 2003 -- The fixed-die placement approach introduced more than 10 years ago was aimed at generating smaller dies compared to the channel-based variable die techniques available at the time. The improvements in terms of quality-of-results ... read more |
| DFT Circuit Designers Battle IC, PC-Board Complexities by in Electronic Design Magazine |
June 16, 2003 -- More so than ever before, complex ICs and the pc boards they populate make design for test (DFT) a basic necessity. Increasing complexity, however, continually challenges DFT designers to keep pace. At one time, IC designers des ... read more |
| It's Time to Get "In the Know" to Tame Nanometer Effects by in Electronic Design Magazine |
June 16, 2003 -- Designers of standard-cell and custom ASICs and SoCs are all understandably excited about the on-going move from 130-nm process technologies to 90-nm processes. Some are planning ahead for further silicon shrinks to 65 nm. And ... read more |
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