January 18, 2007 -- TOOL Corp. and Brion Technologies Inc. today announced the development of an integrated IC design environment that incorporates both TOOL's layout visualization platform, LAVIS, and Brion's OPC and RET/OPC verification system, Tachyon. This integrated environment is an essential tool for semiconductor fabs, photomask shops and fabless IC design houses needing design for manufacturing (DFM) solutions.

TOOL and Brion have combined LAVIS' large-volume data handling and high-speed data display capabilities, which can utilize all the data formats used throughout the chip design processes, with Tachyon, a manufacturing-proven computational lithography platform that is able to execute high-speed, full chip simulation and inspection with high precision. This integrated environment can first display chip design data with LAVIS, conduct lithography simulation of designated areas of that design within Tachyon, and then display the results again with LAVIS. Because design data and simulation parameters are seamlessly and automatically communicated between LAVIS and Tachyon, the user is able to easily obtain simulation results without difficult and complex data preparation.