February 12, 2007 -- OneSpin Solutions GmbH today announced its next-generation 360 EC-FPGA equivalence checking solution. According to OneSpin, this is the industry's first equivalence checker to support all sequential optimizations performed by FPGA synthesis tools on large designs, enabling designers to meet functional, performance and cost targets, with minimal manual intervention. The solution is suitable for both prototyping and production-part verification.

Unlike other established equivalence checkers, synthesis-tool-independent 360 EC-FPGA allows FPGA designers to leverage the optimizations afforded by FPGA synthesis tools and to verify the design "as is," without having to switch off optimizations and undertake extensive manual scripting. In particular, it verifies whole-chip flat netlists, enabling the most aggressive optimizations. It works with established FPGA synthesis tools and flows without any change to the flow. Moreover, the solution does not require the "side files" generated by the synthesis tool, which often are not even validated by equivalence checkers.

The 360 EC-FPGA solution verifies functional equivalence between the register transfer level (RTL) code and the post-synthesis FPGA netlist, as well as between the post-synthesis netlist and the post-place-and-route FPGA netlist. The new equivalence checker supports all major FPGA families from Altera and Xilinx, including netlists generated by the ubiquitous Synplicity Synplify Pro and the Altera Quartus II synthesis flows.

"OneSpin's 360 EC-FPGA shows deep understanding of the sophisticated optimizations performed by Synplicity's FPGA synthesis tools," said Andy Haines, Synplicity's Senior VP of Worldwide Marketing, "bringing extra productivity to our mutual customers."

Majid Ghameshlu, Senior Project Manager Chip Design at Siemens CES added, "360 EC-FPGA secures our FPGA prototyping flow from bugs that might be introduced during synthesis and optimization steps. Its extensive support for sequential optimizations allows us to use more sophisticated synthesis optimizations, resulting in a faster implementation and in better device utilization. 360 EC-FPGA has proven very useful in shortening our debugging cycle."

The 360 EC-FPGA solution also can be deployed with OneSpin's 360 Module Verifier (360 MV) to deliver error-free FPGA-based intellectual property from RTL to FPGA device. The 360 MV static formal verification solution ensures error-free IP, while 360 EC-FPGA preserves this quality through subsequent design phases.

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