March 19, 2007 -- Altium, Ltd. has added a number of productivity-enhancing features to its Altium Designer unified electronics development system to assist engineers with handling high-speed design issues. These new and enhanced features form part of Altium Designer's suite of capabilities aimed to reduce overall design time for high-speed, high-density PCBs, to increase the ease and efficiency for working with high-speed digital signals and to harness the full power of the latest electronic devices and technologies, such as high-capacity programmable logic, that have made their way onto everyday board designs.

Altium has focused recent developments for the latest version of its Altium Designer system — Altium Designer 6 — to include a wide range of high-level interactive and automated tools designed to let all engineers easily assess, manage and troubleshoot signal integrity issues. Altium Designer now adds interactive net length tuning, enhanced board layer navigation and more powerful polygon area fill placement modes to its arsenal of high-speed, high-density capabilities that already includes interactive differential pair routing, impedance-controlled routing, built-in signal integrity analysis and termination matching, automatic BGA escape routing, automatic FPGA board-level pin optimization and full PCB-FPGA bi-directional design synchronization.

Altium Designer's intelligent interactive routing system has been enhanced with the addition of a new interactive length tuning tool specifically for high-speed designs. This new feature lets designers quickly optimize and control net lengths by dynamically inserting 'accordion' segments into a track. Tuning can be manual or rules-driven, and designers can select from a number of amplitude styles available in the system. This feature combines seamlessly with impedance-controlled, differential pair and multi-trace routing capabilities to give Altium Designer users a comprehensive interactive solution tuned for the high-speed, high-density board design projects that are being significantly impacted by modern day programmable devices.

Board navigation has been made more efficient with enhanced control and display over PCB layers, and will deliver significantly enhanced productivity when moving around large complex designs. The placement and editing of polygons has been streamlined to make the creation of large copper-filled areas fast and intuitive. Improvements have also been made to the way components and libraries are identified and used within the system to deliver greater levels of user control and flexibility. Creating and delivering output for designs that contain embedded board arrays has been improved with added intelligence for identifying layer stackup violations. In addition, enhanced output dialogs for Gerber and ODB++ now make it even easier for users to make decisions about whether to proceed with output or resolve compatibility violations.

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