Page loading . . .

  
 Category: News: News Archive 2007: Tuesday, October 21, 2014
OneSpin Solutions Establishes Operations in Japan  
 Printer friendly
 E-Mail Item URL

May 21, 2007 -- Addressing growing customer demand in Japan for its formal verification solutions, OneSpin Solutions GmbH has expanded its global operations with a new sales and field applications engineering office in Yokohama, Japan, known as OneSpin Solutions Japan KK. OneSpin also said it is hiring top Japanese talent for several sales and technical support positions at the new office.

OneSpin offers a complete functional verification solution Ė OneSpin 360 Module Verifier (360MV) Ė to achieve first-time-right, error-free operation and true functional sign-off for a broad range of digital modules and IP, such as peripherals, processors and subsystems of up to a few hundred thousand lines of RTL code. OneSpinís 360MV also completely verifies multiple configurations of configurable IP in one shot, ensuring that each individual configuration functions error-free. Advanced, mature synthesis verification solutions for ASIC, SOC and FPGA design flows complete OneSpinís formal verification product portfolio. According to the company, OneSpin 360 EC-FPGA is the first equivalence checker to support all sequential optimizations performed by FPGA synthesis tools.

Charlie Cump, OneSpinís Vice President of Worldwide Sales commented, "A Japanese office is a mandatory requirement for serving our Japanese customers. It is the next logical step in expanding OneSpinís worldwide sales and support presence."

OneSpinís new operations in Japan are located at the Yokohama World Business Support Center, 6F, Yokohama World Porters, 2-1 Shinkou 2-Chome, Naka-ku, Yokohama 231-0001 Japan.

Go to the OneSpin Solutions GmbH website to find additional information.

E-mail OneSpin Solutions GmbH for more information.

Read more about
OneSpin Solutions GmbH
on SOCcentral.com


Keywords: OneSpin Solutions, functional verification, IP, intellectual property, cores, ASIC design, EDA tools,
571/22804 5/21/2007 953 225
Designer's Mall
Halloween countdown banner
0.734375



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Executive
Viewpoint

Deep Semantic and Formal Analysis


Dr. Pranav Ashar
CTO, Real Intent

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.571  0.796875