November 15, 2007 -- MoSys, Inc. has announced the availability of two new Serial ATA (SATA) Physical Layer (PHY) IPs: MoSys's SATA GEN II PHY IP and GEN I PHY IP. The announcement follows the recent introduction of the Gigabit Ethernet PHY as the latest in the company's portfolio of mixed-signal IP. The SATA PHY IP is targeted at the home entertainment, storage, storage area network (SAN), network attached storage (NAS), and PC markets.

The MoSys SATA GEN II (3.0Gbs) PHY IP is compliant with Serial ATA II Electrical Specification Revision 2.5 and is backward compatible to the widely deployed Gen I (1.5GbS) Serial ATA standard. Key functions integrated into the IP include the use of Out-of-Band Signaling (OOB) protocol for initializing the SATA Interface to execute a pre-defined speed negotiation function. Digital clock and data recovery (CDR) with digital equalization, spread spectrum clocking, optional 8B/10B encoder and decoder, programmable pre-emphasis and swing control, with low power consumption of less than 150mW per channel make the IP ideal for integration into highly complex ASSP, ASICs and SoCs. The SATA Gen II is currently designed in 130-nm General (G) and Low Voltage (LV) CMOS processes and plan to be retargeted to 65-nm and 45-nm process nodes. A complete high speed network to storage solution can now be created utilizing the MoSys Gigabit Ethernet PHY IP together with the SATA GEN II MegaCell.

The Serial ATA Gen I PHY design is compliant with the requirements stated in the Serial ATA standard, rev 1.0a. The IP is designed in 180-nm and 130-nm General (G) processes and can be readily ported to 65-nm and 45-nm technologies. The PHY IP core has an Out-of-Band (OOB) processor to initialize the link, a digital clock and data recovery (CDR) with digital equalization, spread spectrum clocking, optional 8B/10B encoder and decoder at a low power consumption of less than 75mW per channel.

Availability