December 18, 2007 -- ChipX Corp. today announced the introduction of Hybrid ASIC, the implementation of a structured ASIC as IP on a Standard Cell device. This development approach allows for rapid and economical product line development, saving an average of three-to-five hundred thousand dollars in non-recurring engineering (NRE) and tooling costs and enabling the introduction of derivative products two-to-three months faster than today's methodologies allow.

A system-on-chip (SOC) developed in Standard Cell technology results in the smallest device size and best performance, but it incurs significant up-front costs and long manufacturing lead times. Producing a series of custom products becomes capital intensive and often prohibitive for many companies. Structured ASICs solve the problem of high up-front costs and long lead times but the level of integration is often limited to available platforms and sizes. A ChipX Hybrid ASIC gives developers the benefits of Standard Cell and Structured ASICs without the tradeoffs. Turnaround time for logic changes can be as short as 6 weeks, from tape-out to packaged and tested prototypes with NREs starting as low as $99,000 in 0.13micron technology.

"Designers of consumer multimedia products prefer to develop complete product families that give buyers a variety of choices. For example, one member of a video product line might have an H.264 CODEC only while another might add DivX," said Michelle Abraham, Principal Analyst, Multimedia. "Consumer electronic manufacturers could greatly benefit from a fast, inexpensive ASIC methodology that enabled them to implement multiple products, and rapidly enter and dominate new market segments."

"Hybrid ASICs allow our customers to build several generations of customized products or various derivatives quickly and effectively," said Elie Massabki, Vice President of Marketing at ChipX. "For the first time, we can offer a solution that slashes the cost of chip development without introducing compromises."

Typical applications for Hybrid ASIC include video compression or data encryption for designers who wish to implement the same device with different compression or encryption schemes. The implementation of an ASIC with a pre-standard interface or algorithm is also ideal for Hybrid ASIC. In these cases, the potentially variable design logic is placed in the configurable structured ASIC area. A proliferation of new products can quickly and easily be built by changing just the design in this area, without requiring additional work on the fixed portions of the design.

About Hybrid ASIC technology

A Hybrid ASIC combines Standard Cell logic and I/Os, compiled memory and mixed-signal IP with a predefined configurable logic in a Structured ASIC core and configurable memory. The designer decides what functionality is built in the configurable portion of the chip and ChipX customizes a Structured ASIC IP core in any shape (rectangle, L-Shape, etc.) or size (50k gates to 2M gates) desired for the section of the design likely to be altered in the future. Configurable memory blocks and configurable I/Os can also be inserted, offering various levels of flexibility and upgradeability. In the case of a derivative product, only the changing portion of the design needs to be processed. Consequently, development time can be reduced to a fraction of the initial development time — typically tens or hundreds of thousand gates are processed instead of millions of gates — the fabrication time can be reduced to a few layers of metal compared with 30 to 40 layers and the NRE cost is slashed by 70% or more.