Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2006: Friday, May 24, 2013
FPGAs for Prototyping; ASICs for Production   Featured
Publication: EE Times Programmable Logic Designline
Contributor: AMI Semiconductor, Inc. (AMIS)
 Printer friendly
 E-Mail Item URL

March 28, 2006 -- FPGAs are a valuable technology for designing and prototyping digital logic into medium-volume, medium-density applications. Their high unit cost, however, makes an FPGA cost-prohibitive to move into production. Several alternatives exist for taking a digital design implemented with an FPGA into production, including Structured ASICs, cell-based ICs, and gate arrays, all of which offer lower cost, higher performance, lower power consumption, and time-to-market advantages. While the thought of migrating an FPGA design into an ASIC can be overwhelming to a design team, teaming with an experienced ASIC vendor can help ease the process.

Designing a new product in an FPGA allows for design modifications to be made quickly in hardware. Once the design code is stable and the product is ready for production, a migration from an FPGA to a mid range ASIC can cut the production unit cost by one tenth. The low non-recurring engineering (NRE) charges associated with a mid-range ASIC solution coupled with a much lower unit cost make this strategy a powerful tool in achieving low overall costs, giving users a competitive cost advantage in the market.

By Terry Danzer. (Danzer currently serves as AMI Semiconductor’s product marketing engineer for California and major account manager for Cisco Systems worldwide and Alcatel North America and Asia.)


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
AMI Semiconductor, Inc. (AMIS)
on SOCcentral.com

Keywords: EE Times Programmable Logic Designline, AMI Semiconductor (AMIS), structured ASICs, FPGAs,
575/18552 3/28/2006 7776 902


Designer's Mall
0.2773438



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.575  0.328125