July 6, 2006 --At every new process node, IC design becomes more
difficult. But, as design teams contemplate the move to 90- and then
65-nm-process nodes, many are asking whether the increased difficulty is still
just a matter of degree or whether something fundamental is changing. Does a
successful 90-nm-design team differ in some way from a successful 130-nm-design
team? If so, is the change a one-time thing, or are the differences even greater
at 65 nm? The only way to find out is to talk to successful design teams.
Big differences exist in the degree of complexity between the 90- and 65-nm
processes, especially for teams performing cell-based design. A top-level
diagram of the 90-nm flow that fabless-ASIC vendor Open-Silicon uses shows new
branches. Jay Jayaprakash, ASIC-design manager at Open-Silicon, groups the new
challenges at the 90-nm-process node into power, signal integrity, DFM (design
for manufacturability), and DFT (design for test). In the power and
signal-integrity areas, increased complexity for the design team is arguably a
matter of degree. Power management is more critical at the 90-nm node, and it
requires the concerted effort of cell designers, tool designers, logic
designers, and architects. But this situation does not fundamentally differ from
the situation at the 130-nm node. Higher leakage currents at the smaller node
exacerbate the problem. Similarly, signal-integrity analysis is more demanding;
teams must use the available tools and pay heed to their results.
By Ron Wilson, EDN Executive Editor
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.