November 23, 2006 -- The last two decades have seen the emergence of mixed-signal SOC (system-on-chip) design in which one IC integrates both analog and digital blocks. Meanwhile, the IC industry has overwhelmingly moved away from the IDM (independent-device-manufacturer) model in which companies design and manufacture ICs in-house, to the fabless model, in which systems companies design their own ICs but use third-party foundries to manufacture the devices.
As these two trends have matured, driven by Moore's Law, it has become difficult to ensure that the design you develop in your systems house will emerge as a robust chip from the foundry you are targeting. Designers can no longer rely on traditional compact models because they offer a limited description of electrical-device behavior. Due to the broad range of circuit applications implemented by fabless design houses, compact models may fail because they are often applied in ranges exceeding their scope of validity.
The addition of multiple new functions on a chip requires foundries to enhance compact models to address the effects of these additions and to adhere to a standard form that allows multiple companies to use these functions.
By Shye Shapira and Boris Mishori. (Shapira is director of research and development in the RF and mixed-signal product line at Tower Semiconductor, Ltd. and Mishori is the head of Spice modeling and interconnect parasitic extraction at Tower Semiconductor.)
This brief introduction has been excerpted from the original copyrighted article.
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