| A Technical Overview of the CE-ATA Storage Interface by Mentor Graphics Corp. in eeDesign (EE Times EDA News) |
March 20, 2006 -- CE-ATA is the storage industry’s response to providing an optimized standard interface for small form factor (SFF) storage solutions in handheld, portable, and consumer electronics applications. This article presents an overv ... read more |
| FPGAs Poised to Play in Embedded Applications by Mentor Graphics Corp. in DSP-FPGA.com |
March 17, 2006 -- FPGAs have come a long way from their primary use in prototypes. More often, we see them in the final embedded product. The trend among leading FPGA vendors to offer platforms targeting mainstream embedded applications bears wi ... read more |
| The Economics of Structured- and Standard-Cell ASIC Designs by Open-Silicon, Inc. in EDN Magazine |
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March 16, 2006 -- Although structured ASICs promise a shorter
schedule than standard-cell ASICs, this abbreviation comes at a price.
Structured ASICs are more expensive on a per-unit basis, allow less
customization, and offer lower per ... read more |
| Facing the Challenges in Analog Design by Tanner EDA in eeDesign (EE Times EDA News) |
March 13, 2006 -- Analog design has always been a more involved process than digital design. It also takes longer to master, as evidenced by the two to three years needed for a digital designer to gain command of the digital domain versus the ... read more |
| Dealing with PLL Clock Jitter in Advanced Processor Designs: Part 2 by Analog Devices, Inc. (ADI) in EE Times Embedded |
March 8, 2006 -- Without a detailed discussion of PLLs (which, in itself, has little to do with the subject at hand), we can just state that a PLL, being a phase locked loop, is linear in phase and, thus, is linear in jitter.
Although this state ... read more |
| System Synchronization Styles and Trends by Synchronous Design Automation in eeDesign (EE Times EDA News) |
March 6, 2006 -- This article describes emerging trends in synchronizing digital ICs and shows how process scaling, rapid increases in clock frequencies, and demand for lower power dissipation will affect the choice of synchronization styles g ... read more |
| Optimizing Heterogeneous Architectures by Texas Instruments, Inc. (TI) in EDN Magazine |
March 3, 2006 -- The myriad DSP (digital-signal-processing)
applications requiring the performance and integration of SOCs (systems on
chips) - from consumer communications to multimedia products - have created new
challenges for develop ... read more |
| RF-Interference-Design Considerations for Portable-Device Batteries by EDN Magazine |
March 3, 2006 -- Designers face increasing challenges from RFI (radio-frequency interference) when integrating batteries and protection circuitry into systems. At a basic level, a battery pack is an energy-storage device comprising cells and s ... read more |
| Interfacing Electronics to People by EDN Magazine |
March 3, 2006 -- As electronic embedded systems are finding their way into and replacing more mechanical-control systems, it might reasonable to expect to see them finding their way into organic systems, such as the human body. Indeed, electro ... read more |
| Digital Versus Analog Power Control: A Fight to the... Draw? by Electronic Design Magazine |
March 2, 2006 -- The gossip: Analog and digital will soon battle for control of power-supply regulation. The reality: When it comes to feedback-loop control, both approaches seem to happily coexist. Indeed, many vendors offer a choice. Some of ... read more |
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