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 Category: News: News Archive 2008: Thursday, October 27, 2016
Sidense Memory IP Targets Low-Power OTP Applications  
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May 14, 2008 -- Sidense Corp. has announced the Sidense low-power (SLP) one-time programmable (OTP) memory macrocells for low-power and cost-sensitive applications that require highly secure information storage, such as secure key storage, implantable medical devices, RFID, handheld wireless communication devices, analog trimming, and power and energy management.

Based on Sidense's patented split-channel architecture, SLP memory macro implementation requires no additional masks or process steps, thus adding no extra wafer processing cost. Implemented at 180nm, SLP macros are available in densities up to 256 bits and multiple blocks may be stitched together for larger memory capacity. Power dissipation is very low, up to 80% lower power compared to competitive products, an important attribute for low-power applications such as mobile devices. Typical read current for a 256-kbit macro is 0.25µA/MHz/bit with a 2.5-V read voltage. Macro sizes are also very small; a 256-kbit memory takes less than 0.5mm² of silicon.

Additional features

Since Sidense's 1T-OTP bit cells are not based on charge storage for bit programming, data retention is better than 20 years, making the macros a very reliable, long-term embedded storage solution. While the technology is one-time programmable, macros may be used in an emulated multi-time programmable (eMTP) mode through the use of uncommitted memory segments that can later be programmed in the field to update code, security key or other data storage.

The low-power macros feature two additional read modes with enhanced margins and data security for highly reliable, field-programmable systems: differential and redundant read modes. Differential read mode, available in a dual-array configuration only, compares two memory cells, one programmed and one un-programmed, without needing a reference. This provides faster read access times and improved voltage and temperature ranges, ideal for automotive applications. In redundant read mode, two memory cells that are programmed the same are accessed in parallel and compared to a reference voltage, doubling the array's signal margin.

Designers have an optional, configurable IPS (integrated power supply) macro available that can include a charge pump for field-programming memory bits. The IPS macro can also supply the read reference voltage needed for non-differential read operations, eliminating the need for extra circuitry to supply a read reference voltage.

Sidense OTP memory is available at 180nm, 130nm, 90nm and 65nm and scalable to 45nm and below. The IP is available at UMC, TSMC, SMIC, Tower and Chartered. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, medical, automotive, and configurable processors and logic.

Go to the Sidense Corp. website to find additional information.

E-mail Sidense Corp. for more information.

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Sidense Corp.

Keywords: Sidense, IP, intellectual property, cores, nonvolatile memory, non-volatile memory, NVM, one-time-programmable memory, OTP memory, ASIC design,
578/25686 5/14/2008 959 166
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