March 11, 2007 -- Coverage-driven verification (CDV) has generated remarkable interest in recent years. Because of its enormously comprehensive capabilities, more and more verification teams are now relying on the CDV approach. However, implementing a coverage-driven verification environment in a system-level environment requires developing a sequence library, which has proven to be a time-consuming task.
To configure, or reconfigure the library, requires planning for and testing a huge number of interactions with the various portions of the device under test. The challenge poses a significant bottleneck in the verification process of a complex system or device.
A recent project of one of our customers provides a great example. One of their SoCs for use in an HDTV system presented some serious complexity. The SoC included a CPU subsystem, memory manager, and multiple bus interconnects. To test the subsystem, we were looking at more than 6000 register fields - a potential verification bottleneck to say the least.
By Ernst Zwingenberger. (Zwingenberger is currently head of R&D for Verification at El Camino GmbH.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
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