September 4, 2007 -- In recent years the electronic system level (ESL) design methodology has been proposed to solve SoC design problems. SystemC, the main ESL hardware description language, is C++ based with hardware constructs such as modules, ports and clocks. SystemC allows users to model components and systems at higher abstraction levels than Verilog and VHDL. One key feature of SystemC is the transaction level modeling (TLM) that models components and systems at a level higher than the functional level in the sense that the data passing is modeled as transactions instead of signals. By raising the abstraction level we can perform: (1) algorithm/architecture codesign, (2) design space exploration, (3) system level verification, (4) hardware/software co-simulation, and (5) whole-system performance analysis and optimization.
The OCP-IP Consortium has defined a high-performance and bus-independent interface protocol between IPs, usually referred to as the OCP Protocol, which provides a standard for a system designer such that the design time of the core interface can be greatly reduced and possible interface errors can be discovered at the early design stage. OCP defines a point-to-point socket interface specification that enables comprehensive and standardized definitions of a semiconductor IP core's on-chip interface. The IP cores can be a simple peripheral core, a high-performance microprocessor, or an on-chip communication system. Rather than defining rigid signal protocols that a core must implement, the OCP protocol provides a consistent framework for the identification of all kinds of on-chip data, test and control signals for IP cores.
Using OCP, IP designers can make their cores independent of some specific bus protocols, and hence the IP cores will be suitable for any particular design implementation. This makes it easier to reuse OCP-compliant cores across multiple SOC designs. Traditionally designers have to support different bus protocols by modifying a core's interface, the verification suite, the test bench, the documentation, and all other interface-related design issues of the core. OCP eliminates the need to repeatedly modify the core itself, and preserves the verification and test benches by defining all the core's natural interface capabilities in an unchanging, universally understood manner. As a result, significantly improved IP core reusability can be achieved, which leads directly to more predictable and productive SoC designs.
By Chin-Yao Chang, Kuen-Jong Lee, Alan P. Su, and Mark Burton. (Chang and Lee are with the National Cheng Kung University, Taiwan; Su is with SprintSoft, Inc, and Burton is with GreenSocs.)
This brief introduction has been excerpted from the original copyrighted article.
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