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 Category: Magazine & Journal Articles Online: Article Archive 2007: Friday, October 28, 2016
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Utilizing OCP to Design a High Performance Interconnect  by EE Times EDA Designline

January 18, 2007 -- In designing the high-speed interconnect core Z-core InterConnect MIIX, engineers at the Zuken SoC Design Center (now known as Inventure) decided that system performance could be increased using split transaction technology i ... read more

Model Behavior: Creating Embedded-Software Shortcuts  by EDN Magazine

January 18, 2007 -- Embedded systems traditionally have limited processing and memory resources to minimize costs, yet consumer expectations are escalating to include more functions along with auxiliary features, such as high-speed communication ... read more

Beyond Spice: Field-Solver Software Steps in for Modeling High-Frequency, Space-Constrained Circuits  by EDN Magazine

January 18, 2007 -- Spice is a popular circuit simulator. As electronic designs move to higher frequencies and occupy less space, Spice is often insufficient to predict the behavior of even simple circuits. When this scenario occurs, engineers m ... read more

How to Choose the Right FPGA  by Pentek, Inc. in EE Times Signal Processing DesignLine

January 18, 2007 -- FPGAs are a tremendously exciting implementation platform. They are used to replace ASICs, such as digital receivers, and programmable general purpose processors or DSPs. Even though programmable logic has been around for man ... read more

Digital Control Challenges Old Ideas about Power Supply Design  by Analog Devices, Inc. (ADI) in EE Times Power Management Designline

January 17, 2007 -- One of the fundamental decisions required at the beginning of a power supply design is whether to implement voltage-mode control (VMC) or current-mode control (CMC). As with any design, trade-offs exist between both implement ... read more

How to Achieve Faster Compile Times in High-Density FPGAs  by Altera Corp. in EE Times Programmable Logic Designline

January 17, 2007 -- Over the last eight years there has been a 30X increase in logic density and memory bits in FPGA devices. The largest FPGAs such as the recently announced Stratix III EP3SL340 from Altera contain up to 338,000 equivalent ... read more

One-button MATLAB-to-C Conversion  by Catalytic, Inc. in EE Times Signal Processing DesignLine

January 16, 2007 -- For signal processing algorithm developers, MATLAB from The MathWorks is an essential tool. Its vector semantics and powerful visualization capabilities are a necessity for algorithm development. However, since algorithm deve ... read more

How to Maximize FPGA Performance  by Xilinx, Inc. in EE Times Programmable Logic Designline

January 15, 2007 -- As FPGAs push the envelope of performance, understanding how to design for maximum performance requires knowledge of the device architecture and design software. Today's FPGAs resemble a true system-on-a-chip (SOC) with many ... read more

Defining the TLM-to-RTL Design Flow  by Emulation and Verification Engineering (EVE) in EE Times EDA Designline

January 15, 2007 -- As system-on-ship (SOC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron implementation technology hav ... read more

Getting Serious About Transactional Memory  by HPCwire

January 12, 2007 -- The parallelization of computing, via multi-threading cores, multi-core processors and multi-processor systems is encouraging ever greater levels of application concurrency to take advantage of the proliferating CPUs. Multi-c ... read more

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