| Verification IP: Solace for the Common Integration Nightmare? by New Tech Press |
December 24, 2008 -- Language barriers have been problematic since the dawn of civilization. Entire countries have split along spoken language lines, and wars have been fought largely based upon different cultures that have built up around vario ... read more |
| Virtualizing and Securing Your Apps with a Tme-Partitioned RTOS by LynuxWorks, Inc. in EE Times Embedded |
December 22, 2008 -- The advances made in multi-core technology and associated middleware allow developers to combine the best principles of multi-processing, virtualization, real-time and hard partitioning to create a highly optimized execution ... read more |
| Using Requirements Based Testing to Find Defects in Your Software Builds by EE Times Embedded |
December 18, 2009 -- Our primary job, as QA and testing professionals, is to find defects in software builds. Fortunately, however, most of us have moved beyond exposing and tracking bugs to the more critical role of ensuring that the software o ... read more |
| Planning, Adopting and Implementing Adaptive Reuse by Integrated Device Technology, Inc. (IDT) in EE Times EDA Designline |
December 16, 2008 -- It has been mentioned that during the rough-and-tumble days of 1950s Chicago politics, a ward boss asked an Adlai Stevenson volunteer who sent him to help in the campaign and when the response was nobody, he quickly replied: ... read more |
| Introduction to Low-Power Design by Analog Devices, Inc. (ADI) in EE Times Signal Processing DesignLine |
December 10, 2008 -- No embedded design is complete without a thorough analysis of power. This goes without saying for battery-operated devices, but it also holds true for wired systems. Power has thermal, volumetric, and financial impacts in al ... read more |
| Use Algorithmic Synthesis to Solve Your FPGA Prototyping and Design Issues by Synfora, Inc. in Electronic Design Magazine |
December 10, 2008 -- Algorithmic synthesis—the efficient implementation of algorithms in silicon—offers compelling value to both system-on-chip (SOC) and FPGA design teams. However, there are subtle but important differences in the teams’ requir ... read more |
| How to Exploit the Uniqueness of FPGA Silicon for Security Applications by Verayo, Inc. in EE Times Programmable Logic Designline |
December 10, 2008 -- FPGAs are used in place of ASICs for an increasing number of applications. Traditionally seen primarily as devices with programmable gates, FPGAs have progressively evolved since year 2000 into "platform" devices with many i ... read more |
| Algorithmic Synthesis for Video Post-Processor Design by Synfora, Inc. in EE Times EDA Designline |
December 9, 2008 -- With growing consumer demand for faster, cheaper and more complex devices, designers face constant pressure to meet time-to-market deadlines and financial constraints. The need to integrate ever more functionality into a prod ... read more |
| Designing Protective Circuitry for DSL loops: Beware of Pitfalls by EDN Magazine |
December 5, 2008 -- The appropriate protective-circuit design for DSL (digital-subscriber-line) loops depends on the type of loop: Loops vary in voltage conditions and in susceptibility to attenuation and degradation in signal integrity. Therefo ... read more |
| Verification Metrics: When is Enough Enough? by EDN Magazine |
December 5, 2008 -- Today, most design managers depend on some sort of verification-coverage metrics to answer three primary questions, according to Mentor Graphics' chief verification scientist, Harry Foster: Where have I been, where am I going ... read more |
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