March 4, 2008 -- Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase. Starting with the techniques for lowering the power consumption in analog circuits such as operational amplifiers, this article will then focus on low power design for high speed serial interconnects. Different architectures for output drivers and methods such as level shifting, for ac-coupled systems such as PCI Express, SATA, and XAUI will be discussed.

In the design of analog/mixed-signal IP many factors contribute to the overall consumption of power. The common methods include:

Simplifying the complexity of the circuit and using folded designs exploiting the complementary properties of NMOS and PMOS devices. Taking conventional architectures and converting them into designs that consume less power with adaptive biasing. Gearing the integrated circuit technology towards low power performance by using high Vt processes for example 65nm LP or 40nm LP. Although this may not necessarily reduce power in the active mode as more current is needed to drive the high speed transmitter in the slower, low power technologies. Decreasing transistor dimensions together with lowering the supply voltage.

By Navraj Nandra. (Nandra is Director of Product Marketing for the mixed-signal products that include SerDes, USB and DDR2 at Synopsys, Inc.)