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 Category: Magazine & Journal Articles Online: Article Archive 2008: Wednesday, June 19, 2013
How to Defend Against The Cloning of Your FPGA Designs  
Publication: EE Times Programmable Logic Designline
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September 17, 2008 -- This article describes a new way of tagging designs to help to counter the rapidly growing trade in stolen IP and cloned designs. The topic is a difficult one for the industry to discuss; recently, however, more and more voices have been raised on the issue.

By Paul Dillien. (Dillon is the founder of the high-technology marketing consultancy company High Tech Marketing.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Keywords: EE Times Programmable Logic Designline, FPGAs, field programmable gate arrays, IP, intellectual property, cores,
580/26978 9/17/2008 6749 315
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