|Publication: Components in Electronics (CIE)|
Contributor: SpringSoft, Inc.
October 1, 2008 -- Verification tools and methodologies have both evolved and undergone revolutionary changes, and both are equally as important to stay abreast of Moore’s law. Complex SOC designs can be implemented by acquiring third-party intellectual property (IP), a divide and conquer approach within development teams, and, of course, by adding more designers. Verification, on the other hand, must deal with the large designs as a whole. This burden falls on the underlying verification tools and associated methodologies that must be able to "simulate" a model of the design, often at different levels of abstraction.
Fortunately, assertion-based verification enables a revolutionary methodology change that addresses this ever-increasing burden by adding ‘observability’ (result checking) and testing (development of actual tests) into the verification environment.
By Amanda Hsiao. (Hsiao is Technical Marketing Manager at Spingsoft, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Components in Electronics (CIE) website.
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|Keywords: Components in Electronics (CIE), SpringSoft, ASICs, ASIC design, IP, intellectual property, cores, verification, system-on-chip, SoC, EDA tools, |
|580/27361 10/1/2008 7620 296|