November 25, 2008 -- Moore's Law continues to drive chip complexity and performance to new highs, while stressing and periodically "breaking" existing design flows. Fortunately for consumers of electronic design automation (EDA) tools, the same shrinking geometries that make their design problems tougher are also helping to improve the performance of these tools.
But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches, such as hardware description language (HDL) simulation, continue to lose ground. HDL simulation speeds aren't keeping pace with device complexity because many new devices -- 3G cell phones, internet routers and image processors, for example -- require massive verification sequences that would take many years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software to fully verify a new system on chip (SoC) or system design.
Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a causality dilemma: which comes first -- the "final" hardware or the "final" software?
In recent years, a new breed of tools, collectively called platforms based on a high-level of design abstraction, have been introduced in an attempt to start software validation well ahead of silicon availability.
By Lauro Rizzatti. (Rizzatti is General Manager of EVE-USA.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.