December 10, 2008 -- Algorithmic synthesis—the efficient implementation of algorithms in silicon—offers compelling value to both system-on-chip (SOC) and FPGA design teams. However, there are subtle but important differences in the teams’ requirements when using algorithmic synthesis tools. This is especially true for FPGAs, which can be designed as just one in a series of steps to creating an SoC or as production-ready devices.

The different requirements and different expertise of each team lead to different demands on the synthesis tools. In both SOCs and FPGAs, the algorithms define and differentiate the end product. Algorithmic synthesis is used to deliver efficient hardware implementations of these algorithms in silicon to create the key PPA (performance, power, and area) characteristics. There are two main uses for algorithmic synthesis tools when applied to FPGAs:

FPGA design: the development of a device that will be directly used in a final product. The applications for FPGA design include high-end TVs, wireless basestations, and medical imaging systems. FPGA-dedicated design teams complete these designs.

FPGA prototyping: the use of an FPGA to assist in verifying the RTL to be implemented on an SOC. In this case, the FPGA primarily is used to verify the SOC RTL, with the results considered in relation to the SOoC design. The inefficiency of the FPGA implementation itself isn’t a major consideration. The needs for SOC designers using FPGA prototyping are the same as for the rest of the SOC.

By Simon Napper. (Napper is president and CEO of Synfora, Inc.)