| Simplifying PLL Design by Cadence Design Systems, Inc. in EE Times EDA Designline |
February 12, 2008 -- Phase lock loops (PLLs) play a key role in today's thriving RF industry. Commonly employed to address various timing requirements in ASIC designs, these basic building blocks allow designers to multiply clock frequencies, co ... read more |
| Hardware Design Using ESL by Calypto Design Systems, Inc. in Electronic Engineering Times (EE Times) |
February 11, 2008 -- To build increasingly sophisticated chips, engineers must be freed from low-level details and limiting methodologies. ESL design flows raise the level of abstraction from the register transfer level (RTL) to the system level ... read more |
| Physically Aware Test Development by Magma Design Automation, Inc. in EE Times EDA Designline |
February 5, 2008 -- As designs move to smaller nanometer processes, test development is becoming more difficult, effectively impeding product release. Not only are test sets growing at a very high rate, but they are unable to provide adequate le ... read more |
| Revving Up with Automotive Multicore by NEC Electronics America, Inc. in EDN Magazine |
February 5, 2008 -- Although many embedded applications can afford custom and semi-custom solutions that allow SOCs (system-on-chip) to be tuned for specific functionality and performance, the unit-cost sensitivity of the automotive market drive ... read more |
| FPGA-Based Prototyping: "Productivity to Burn" by Xilinx, Inc. in EE Times Programmable Logic Designline |
January 30, 2008 -- These days, a large portion of ASIC, SOC, and ASSP designs are at least partially prototyped in one or more FPGAs. This amounts to many thousands of prototyping projects per year. Compared with other ASIC verification methods ... read more |
| Power Integrity and Energy-Aware Floor Planning by Anasim Corp. in EE Times EDA Designline |
January 29, 2008 -- We have heard so much about floor planning for integrated circuits – routing, timing awareness, and even leakage and temperature awareness; how often do we come across the term Roof Planning in SoC's? Yet, just as the foundat ... read more |
| mAgic DSP Ooptimization, Part 2: Writing C Code by Atmel Corp. in EE Times Signal Processing DesignLine |
January 28, 2008 -- In the first part of this two part series, we outlined the main reasons we designed the mAgic DSP architecture with C programmability in mind. In this article we'll explore how to get the most out of the mAgic architecture by ... read more |
| Choosing System-on-Chip Processes: A Tough Decision by EDN Magazine |
January 24, 2008 -- An unwritten assumption of the chip-design profession is that it is always best to use the newest available process: best for your résumé, and best for the design. The most advanced process you can get will make the chip fast ... read more |
| Software Considerations Around RapidIO Designs by Fabric Embedded Tools Corp. in EDN Magazine |
January 24, 2008 -- In general, the topic of software is rather vast. It ranges from low-level drivers, RTOSs, through to applications. However, there are some unique software considerations that are specific to RapidIO. This article will provid ... read more |
| mAgic DSP Optimization, Part 1: Hardware/Software Co-Development by Atmel Corp. in EE Times Signal Processing DesignLine |
January 21, 2008 -- Developing a powerful new DSP is no easy feat. To be successful, developers must strike a delicate balance between often conflicting requirements. A DSP must offer competitive performance for its target applications. It must ... read more |
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