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 Category: News: News Archive 2009: Thursday, April 17, 2014
Intilop Announces Customization Services for Its TCP-Offload Engine SOC IP   
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March 3, 2009 -- Intilop, Inc. has announced addition of value-added customization services to its TCP offload engine (TOE) solutions that are integrated with ARP hardware module, G Bit Ethernet MAC and AMBA 2.0 bus interfaces running at 2-Gbps sustained rates.

All of connection, packet transfer, disconnection, session management overhead, which traditionally is performed by TCP/IP software, is accomplished by this TOE. It is a new paradigm and new level of integration in networking hardware acceleration. It implements control plane and data plane processing of TCP/IP in hardware that are 10 to 20X faster than TCP/IP software stack.

Because of its advanced scalable architecture, the TOE can be customized to implement differentiated features and performance requirements to meet customer’s specifications such as miscellaneous protocol processing and monitoring at G-bit line rate, in addition to TCP/IP, ARP module, number of simultaneous connections, TCP/IP performance tuning based upon type of network/traffic and application usage, scalable packet FIFO size, scalable size of Session Management table, Session Parameters, scalable size of direct store Packet memories, integrated DDR/SSRAM controllers, choice of PHY interface, and more.

This integrated TOE silicon IP with customizable features provides enhanced functionality in all networking equipment including Layer-2-5 switches/routers, IPS/IDS appliances and network security appliances, severs and high end NICs. An advanced architecture with built-in scalability allows targeting to many silicon libraries from FPGAs to 0.18-µm-0.090-nm ASICs without compromising performance or functionality.

Go to the Intelop, Inc. website for details.

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Keywords: Intilop, ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, TCP/IP,
589/28180 3/3/2009 2792 124
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