Page loading . . .

 Category: News: News Archive 2009: Tuesday, October 25, 2016
Magma Announces Talus Support of Common Power Format  
 Printer friendly
 E-Mail Item URL

April 27, 2009 -- Magma Design Automation, Inc. has enhanced the Talus IC implementation system to support the Common Power Format (CPF). With the addition of CPF, Talus becomes the first RTL-to-GDSII flow to support both the CPF and the Unified Power Format (UPF). Both formats enable better, faster, low-power IC implementation by allowing specifications to be captured just once and used consistently throughout the flow. By supporting both formats, Magma offers designers the flexibility to choose the low-power format that best suits their designs while also providing advanced low-power design capabilities that minimize power consumption, maximize quality of results and reduce iterations.

Magma's open architecture and unified data model simplified the implementation of the CPF across the Talus RTL-to-GDSII environment. With its implementation and analysis engines sharing a single, common view of the design and CPF support, Talus enables designers to implement low-power design techniques throughout the flow.

"All applications, not just wireless and portable consumer devices, are driving the demand for lower power, lower cost ICs," said Premal Buch, General Manager of Magma's Design Implementation Business Unit. "To help meet these demands, Talus provides a flow that offers advanced low-power design techniques, including automated multi-voltage design, ultra-low-power clock tree synthesis and physical implementation, that meet dynamic and leakage power requirements while reducing turnaround time. By adding support for CPF we are being responsive to requests from our users and enabling them to take advantage of the additional time savings through use of the low-power format of their choice."

Talus low-power design flow

The Talus implementation system provides a fully integrated RTL-to-GDSII flow for high-performance, high-complexity, low-power nanometer designs. Talus Design, Hydra and Talus Vortex are key components of the system. Talus Design is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process, and automates data-path synthesis and floorplan generation for prototyping. Hydra is an advanced floorplan synthesis and hierarchical design planning product with physical optimization capabilities that delivers superior predictability. Talus Vortex is a physical design environment that delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows.

Talus Power Pro works in conjunction with Talus Design, Hydra and Talus Vortex to enable optimal power management throughout the flow. It features power-aware synthesis, physical optimization, clock tree synthesis and routing, allowing designers to minimize power and ensure uniform power distribution.

Talus Power Pro reads in the power constraints from the CPF file at the beginning of the RTL-to-GDSII flow. Power constraints such as clock gating, retention-flop synthesis and multi-Vdd domain definitions can be defined for dynamic power reduction. Special cells such as level shifters and isolation cells can be inferred during the synthesis stage to support multi-Vdd flows. For domains that are powered down, switches can be inferred at the RTL stage to facilitate simulation. State tables can be used to define the relationship between the different domains that have been created. Talus Power Pro can also write out CPF files at any point in the design flow for easy interoperability with third-party tools.

Go to the Magma Design Automation, Inc. website to find additional information.

E-mail Magma Design Automation, Inc. for more information.

Read more about
Magma Design Automation, Inc.

Keywords: Magma Design Automation, ASICs, ASIC design, power analysis, power optimization, low power design, low-power design, Common Power Format, CPF, Unified Power Format, UPF, EDA tools,
589/28623 4/27/2009 3984 191
Designer's Mall

 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.589  0.59375