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 Category: News: News Archive 2009: Friday, October 31, 2014
eASIC Accelerates DSP Efforts with New IP Cores  
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May 7, 2009 -- eASIC Corp. has announced the immediate availability of two new DSP IP cores, an FFT and FIR filter compiler, to accelerate itís move into the high-performance DSP market. The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100Msps with a compact footprint. The FIR Compiler core, available from eZ-IP Alliance partner Steepest Ascent can process data streams as high as 500Msps and with its optimized multiplier-less architecture is perfectly suited to Nextreme and Nextreme-2 architectures.

The addition of mainstream DSP blocks to eASICís IP portfolio makes it easier for wireless and video/ imaging system designers to rapidly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series New ASICs.

FFT and FIR filters are the most widely used algorithms in digital communications and video/ imaging systems. The new FIR filter compiler lets designers generate optimal implementations of single or multi-rate filters and also takes advantage of multi-channel applications. Most importantly, the optimized multiplier-less architecture greatly reduces resource usage, boosts performance and eliminates the need for large amounts of hard multipliers typically found in FPGAs today. The FFT core provides optimal implementations for OFDM wireless systems such as LTE & WiMAX. Both IP cores support Nextreme and Nextreme-2 New ASICs.

"Many wireless infrastructure and video/ imaging designers that are using FPGAs are desperately looking for ways to significantly reduce cost and power consumption of their systems," said Jasbinder Bhoot, Vice President of Marketing at eASIC. "This new IP portfolio will make it much simpler and quicker for customers to migrate their expensive and power hungry FPGA-based DSP designs to Nextreme Series New ASICs and reduce both power consumption and cost.Ē

"We are very pleased to be a part of the eASIC eZ-IP Alliance and make our wireless expertise available to designers hungry to reduce cost and power. Our FIR compiler is an optimal design and perfectly suited to the eASIC architecture. We are confident that wireless designers will leverage this IP to replace any FPGA style FIR filters they are using," said Dr Garrey Rice, Head of HDL Design at Steepest Ascent.

Go to the eASIC Corp. website for details.

E-mail eASIC Corp. for more information.

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Keywords: eASIC, structured ASICs, DSP, digital signal processing, IP, intellectual property, cores,
589/28671 5/7/2009 3101 193
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