May 7, 2009 -- eASIC Corp. has announced the immediate availability of two new DSP IP cores, an FFT and FIR filter compiler, to accelerate it’s move into the high-performance DSP market. The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100Msps with a compact footprint. The FIR Compiler core, available from eZ-IP Alliance partner Steepest Ascent can process data streams as high as 500Msps and with its optimized multiplier-less architecture is perfectly suited to Nextreme and Nextreme-2 architectures.

The addition of mainstream DSP blocks to eASIC’s IP portfolio makes it easier for wireless and video/ imaging system designers to rapidly migrate costly FPGA-based DSP designs to lower-cost, lower-power Nextreme Series New ASICs.

FFT and FIR filters are the most widely used algorithms in digital communications and video/ imaging systems. The new FIR filter compiler lets designers generate optimal implementations of single or multi-rate filters and also takes advantage of multi-channel applications. Most importantly, the optimized multiplier-less architecture greatly reduces resource usage, boosts performance and eliminates the need for large amounts of hard multipliers typically found in FPGAs today. The FFT core provides optimal implementations for OFDM wireless systems such as LTE & WiMAX. Both IP cores support Nextreme and Nextreme-2 New ASICs.

"Many wireless infrastructure and video/ imaging designers that are using FPGAs are desperately looking for ways to significantly reduce cost and power consumption of their systems," said Jasbinder Bhoot, Vice President of Marketing at eASIC. "This new IP portfolio will make it much simpler and quicker for customers to migrate their expensive and power hungry FPGA-based DSP designs to Nextreme Series New ASICs and reduce both power consumption and cost.”