June 10, 2009 -- Azuro, Inc. has announced the inclusion of its PowerCentric low power clock tree synthesis tool in TSMC's new Integrated Sign-Off Flow. The Integrated Sign-Off Flow is an automated RTL to GDSII chip implementation flow that tightly integrates TSMC foundry technology files, pre-qualified library, IP, EDA tools, and sign-off margin recommendations into a fully automated scripted production-quality flow that has been proven and refined over hundreds of applications.
"Rising design setup costs and design cycle times are critical challenges for the semiconductor industry," said S.T. Juang, Senior Director of Design Infrastructure Marketing at TSMC. "The TSMC Integrated Sign-Off Flow brings together parties across the entire chip design ecosystem into a tightly controlled fully automated platform for achieving best in class silicon quickly and with lowest cost."
Azuro and TSMC worked closely during the development and beta testing of the Integrated Sign-Off Flow to ensure that the insertion of PowerCentric into the Flow was completely transparent to flow users. Using the Integrated Sign-Off Flow, chip design teams taping out to TSMC's foundries can adopt Azuro's low-power CTS capability within an extensively pre-tested pre-integrated production-ready flow including a full set of automated scripts and user documentation.
Go to the Azuro, Inc. website to find additional information.
