Page loading . . .

  
 Category: News: News Archive 2009: Thursday, May 23, 2013
CoWare and Tensilica Deliver Software-Development Solution for Multi-Core Tensilica-Based Platforms  
 Printer friendly
 E-Mail Item URL

December 16, 2009 -- CoWare, Inc. and Tensilica, Inc., the leading provider of configurable dataplane processor cores (DPUs), have collaborated to further enhance the integration of Tensilica's processor models into the CoWare tools to support CoWare's advanced functionality to ease software development on multi-core Tensilica-based SOC (system-on-chip) designs. The enhanced solution is being used by joint CoWare-Tensilica customers in automotive, consumer and wireless markets.

CoWare virtual platforms are the virtualized representation of an electronic system used for the purpose of software development. It removes the dependency on the availability of expensive hardware prototypes and development test benches and provides cost-effective software development capabilities for debugging and analysis. The updated integration of Tensilica's DPUs enables:
  • Enhanced debug visibility combining CoWare Virtual Platform Analyzer with Tensilica's software debugger;
  • Reproducibility and predictability through a full scripting environment;
  • High-speed simulation performance for the Tensilica subsystem thanks to the TurboXim mode of Tensilica's ISS models;
  • Multi-core software development solution through debug synchronization and debug and analysis visibility across all cores in the system.

The joint CoWare-Tensilica Processor Support Package (PSP) solution has been actively used by developers worldwide to explore the best architecture for a given application combining the versatility of the Tensilica cores with the architecture design solution from CoWare. This joint solution has been significantly enhanced to address the increased software development challenges of today's multi-core designs. The unique combination of features, targeting the architect as well as the software developer, enables the joint solution to be used throughout the design process starting from the definition phase, then the development phase through to the deployment phase.

"CoWare's Electronic System Virtualization (ESV) tools have been widely adopted by some of our largest customers," said Steve Roddy, Vice President of Marketing, Tensilica. "Software development on multi-core designs is becoming increasingly critical to create differentiating products. Our partnership with CoWare is offering joint customers a unique solution to cope with the complexity and significantly pull in the design schedule with the ability to develop software before the hardware is available."

"Tensilica cores are being used in a wide variety of applications," said Marc Serughetti, Vice President of Marketing and Business Development at CoWare. "The power and flexibility of the configurable cores enables designers to combine multiple versions of the Tensilica cores in one design. The partnership between our two companies addresses multi-processor platform exploration and reuse, and early software development – by providing the best design and software development environment for our joint users."

Availability

Tensilica Xtensa and Diamond Standard PSPs are available immediately from CoWare as part of the CoWare Model Library. For more information on these PSPs, CoWare Virtual Platform, CoWare Platform Architect, CoWare Model Library, and CoWare's other products, visit the CoWare website. For more information on the Tensilica Xtensa and Diamond Standard DPUs, visit the Tensilica website.

Go to the CoWare, Inc. website to find additional information.

E-mail CoWare, Inc. for more information.

Read more about
CoWare, Inc.
and
Tensilica, Inc.
on SOCcentral.com


Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, electronic system level design, ESL, IP, intellectual property, cores, microprocessors, MPUs, configurable processors, reconfigurable computing, CoWare, Tensilica,
589/30333 12/18/2009 3693 168


Designer's Mall
0.390625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.589  0.46875