February 19, 2009 -- Once upon a time, you verified a logic design for an FPGA by compiling it, loading it, and pushing the reset button on your evaluation board. But, as FPGAs have become larger, this "blow-and-go" verification style, as Xilinx’s director of software-product marketing, Hitesh Patel, terms it, has become counterproductive. The odds of creating a multimillion-gate design so close to perfection that you could debug it from the pins on the package are vanishingly small. So, design teams have begun to employ software-based simulation of the design, much as ASIC teams have done for years.
But this approach raises a series of important questions: Should the role of simulation in an FPGA design be the same as it is in an ASIC design? Should the verification team still, at some point, just put the design in the target FPGA and start testing it at speed? If so, when is that point? To find out what design teams are doing today, we asked some of the people who work most closely with FPGA users. And, for reference, we asked a few ASIC design teams who use FPGA prototypes in their verification processes for their views, as well.
By Ron Wilson, Executive Editor EDN.
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.