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 Category: Magazine & Journal Articles Online: Article Archive 2009: Sunday, October 23, 2016
High-Level Synthesis of JPEG Application Engine  
Publication: Design & Reuse
Contributor: HCL Technologies, Ltd.
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May 25, 2009 -- High-Level Synthesis (HLS) technology and tools are used to transform high-level behavioral model written in C, to synthesizable hardware in RTL . We have evaluated one such commercial HLS tool to create JPEG encoder RTL straight from C algorithm within a very short design time. This paper discusses the steps involved in automatic "algorithm-to-RTL" transformation and compares the results with RTL developed using traditional method.

By Pragnajit Datta Roy , Sameer Arora, Rajiv Kumar Gupta and Anil Kamboj. (All are with HCL Technologies, Ltd., Noida, India.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the Design & Reuse website.

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HCL Technologies, Ltd.

Keywords: Design & Reuse, HCL Technologies, ASICs, ASIC design, JPEG, behavioral synthesis, RTL, C, EDA tools,
590/28799 5/25/2009 6860 454
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